// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family Main Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x400000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
l3cache-sram@200000 {
reg = <0x200000 0x200000>;
};
};
scm_conf: syscon@104000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00104000 0x00 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
u
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