path: root/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>

/ {
	serdes_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x400000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x400000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		tifs-sram@1f0000 {
			reg = <0x1f0000 0x10000>;
		};

		l3cache-sram@200000 {
			reg = <0x200000 0x200000>;
		};
	};

	scm_conf: syscon@104000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0x00 0x00104000 0x00 0x18000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x00104000 0x18000>;

		usb_serdes_mux: mux-controller@0 {
			compatible = "mmio-mux";
			reg = <0x0 0x4>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
		};

		serdes_ln_ctrl: mux-controller@80 {
			compatible = "mmio-mux";
			reg = <0x80 0x10>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
					<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
		};
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
		      <0x00 0x6f020000 0x00 0x2000>;   /* GICV */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&sms>;
		ti,sci-dev-id = <148>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x120>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x00 0x04e00000 0x00 0x1200>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;

		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
		       <&main_udmap 0x4a41>;
		dma-names = "tx", "rx1", "rx2";

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x00 0x04e10000 0x00 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	main_timer0: timer@2400000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2400000 0x00 0x400>;
		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 63 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 63 1>;
		assigned-clock-parents = <&k3_clks 63 2>;
		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer1: timer@2410000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2410000 0x00 0x400>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 64 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 64 1>;
		assigned-clock-parents = <&k3_clks 64 2>;
		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer2: timer@2420000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2420000 0x00 0x400>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 65 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 65 1>;
		assigned-clock-parents = <&k3_clks 65 2>;
		power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer3: timer@2430000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2430000 0x00 0x400>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 66 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 66 1>;
		assigned-clock-parents = <&k3_clks 66 2>;
		power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer4: timer@2440000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2440000 0x00 0x400>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 67 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 67 1>;
		assigned-clock-parents = <&k3_clks 67 2>;
		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer5: timer@2450000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2450000 0x00 0x400>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 68 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 68 1>;
		assigned-clock-parents = <&k3_clks 68 2>;
		power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer6: timer@2460000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2460000 0x00 0x400>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 69 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 69 1>;
		assigned-clock-parents = <&k3_clks 69 2>;
		power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer7: timer@2470000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2470000 0x00 0x400>;
		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 70 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 70 1>;
		assigned-clock-parents = <&k3_clks 70 2>;
		power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer8: timer@2480000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2480000 0x00 0x400>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 71 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 71 1>;
		assigned-clock-parents = <&k3_clks 71 2>;
		power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer9: timer@2490000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x2490000 0x00 0x400>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 72 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 72 1>;
		assigned-clock-parents = <&k3_clks 72 2>;
		power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer10: timer@24a0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24a0000 0x00 0x400>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 73 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 73 1>;
		assigned-clock-parents = <&k3_clks 73 2>;
		power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main_timer11: timer@24b0000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x24b0000 0x00 0x400>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 74 1>;
		clock-names = "fck";
		assigned-clocks = <&k3_clks 74 1>;
		assigned-clock-parents = <&k3_clks 74 2>;
		power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
	};

	main