/*
* Performance events - AMD IBS
*
* Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
*
* For licencing details see kernel-base/COPYING
*/
#include <linux/perf_event.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/ptrace.h>
#include <linux/syscore_ops.h>
#include <linux/sched/clock.h>
#include <asm/apic.h>
#include "../perf_event.h"
static u32 ibs_caps;
#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
#include <linux/kprobes.h>
#include <linux/hardirq.h>
#include <asm/nmi.h>
#include <asm/amd-ibs.h>
#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
/*
* IBS states:
*
* ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
* and any further add()s must fail.
*
* STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
* complicated by the fact that the IBS hardware can send late NMIs (ie. after
* we've cleared the EN bit).
*
* In order to consume these late NMIs we have the STOPPED state, any NMI that
* happens after we've cleared the EN state will clear this bit and report the
* NMI handled (this is fundamentally racy in the face or multiple NMI sources,
* someone else can consume our BIT and our NMI will go unhandled).
