path: root/arch/x86/include/asm/msr-index.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_MSR_INDEX_H
#define _ASM_X86_MSR_INDEX_H

#include <linux/bits.h>

/* CPU model specific register (MSR) numbers. */

/* x86-64 specific MSRs */
#define MSR_EFER		0xc0000080 /* extended feature register */
#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
#define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
#define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */

/* EFER bits: */
#define _EFER_SCE		0  /* SYSCALL/SYSRET */
#define _EFER_LME		8  /* Long mode enable */
#define _EFER_LMA		10 /* Long mode active (read-only) */
#define _EFER_NX		11 /* No execute enable */
#define _EFER_SVME		12 /* Enable virtualization */
#define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
#define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */
#define _EFER_AUTOIBRS		21 /* Enable Automatic IBRS */

#define EFER_SCE		(1<<_EFER_SCE)
#define EFER_LME		(1<<_EFER_LME)
#define EFER_LMA		(1<<_EFER_LMA)
#define EFER_NX			(1<<_EFER_NX)
#define EFER_SVME		(1<<_EFER_SVME)
#define EFER_LMSLE		(1<<_EFER_LMSLE)
#define EFER_FFXSR		(1<<_EFER_FFXSR)
#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)

/* FRED MSRs */
#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */
#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */
#define MSR_IA32_FRED_RSP2	0x1ce			/* Level 2 stack pointer */
#define MSR_IA32_FRED_RSP3	0x1cf			/* Level 3 stack pointer */
#define MSR_IA32_FRED_STKLVLS	0x1d0			/* Exception stack levels */
#define MSR_IA32_FRED_SSP0	MSR_IA32_PL0_SSP	/* Level 0 shadow stack pointer */
#define MSR_IA32_FRED_SSP1	0x1d1			/* Level 1 shadow stack pointer */
#define MSR_IA32_FRED_SSP2	0x1d2			/* Level 2 shadow stack pointer */
#define MSR_IA32_FRED_SSP3	0x1d3			/* Level 3 shadow stack pointer */
#define MSR_IA32_FRED_CONFIG	0x1d4			/* Entrypoint and interrupt stack level */

/* Intel MSRs. Some also available on other CPUs */
#define MSR_TEST_CTRL				0x00000033
#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29
#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)

#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
#define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
#define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
#define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
#define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
#define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
#define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */
#define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
#define SPEC_CTRL_BHI_DIS_S_SHIFT	10	   /* Disable Branch History Injection behavior */
#define SPEC_CTRL_BHI_DIS_S		BIT(SPEC_CTRL_BHI_DIS_S_SHIFT)

/* A mask for bits which the kernel toggles when controlling mitigations */
#define SPEC_CTRL_MITIGATIONS_MASK	(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
							| SPEC_CTRL_RRSBA_DIS_S \
							| SPEC_CTRL_BHI_DIS_S)

#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
#define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
#define PRED_CMD_SBPB			BIT(7)	   /* Selective Branch Prediction Barrier */

#define MSR_PPIN_CTL			0x0000004e
#define MSR_PPIN			0x0000004f

#define MSR_IA32_PERFCTR0		0x000000c1
#define MSR_IA32_PERFCTR1		0x000000c2
#define MSR_FSB_FREQ			0x000000cd
#define MSR_PLATFORM_INFO		0x000000ce
#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
#define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)

#define MSR_IA32_UMWAIT_CONTROL			0xe1
#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)
#define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)
/*
 * The time field is bit[31:2], but representing a 32bit value with
 * bit[1:0] zero.
 */
#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)

/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
#define MSR_IA32_CORE_CAPS			  0x000000cf
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT	  2
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS	  BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)

#define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
#define NHM_C3_AUTO_DEMOTE		(1UL << 25)
#define NHM_C1_AUTO_DEMOTE		(1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)
#define SNB_C3_AUTO_UNDEMOTE		(1UL << 27)
#define SNB_C1_AUTO_UNDEMOTE		(1UL << 28)

#define MSR_MTRRcap			0x000000fe

#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
#define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */
#define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */
#define ARCH_CAP_RSBA			BIT(2)	/* RET may use alternative branch predictors */
#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */
#define ARCH_CAP_SSB_NO			BIT(4)	/*
						 * Not susceptible to Speculative Store Bypass
						 * attack, so no Speculative Store Bypass
						 * control required.
						 */
#define ARCH_CAP_MDS_NO			BIT(5)   /*
						  * Not susceptible to
						  * Microarchitectural Data
						  * Sampling (MDS) vulnerabilities.
						  */
#define ARCH_CAP_PSCHANGE_MC_NO		BIT(6)	 /*
						  * The processor is not susceptible to a
						  * machine check error due to modifying the
						  * code page size along with either the
						  * physical address or cache type
						  * without TLB invalidation.
						  */
#define ARCH_CAP_TSX_CTRL_MSR		BIT(7)	/* MSR for TSX control is available. */
#define ARCH_CAP_TAA_NO			BIT(8)	/*
						 * Not susceptible to
						 * TSX Async Abort (TAA) vulnerabilities.
						 */
#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
						 * Not susceptible to SBDR and SSDP
						 * variants of Processor MMIO stale data
						 * vulnerabilities.
						 */
#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
						 * Not susceptible to FBSDP variant of
						 * Processor MMIO stale data
						 * vulnerabilities.
						 */
#define ARCH_CAP_PSDP_NO		BIT(15)	/*
						 * Not susceptible to PSDP variant of
						 * Processor MMIO stale data
						 * vulnerabilities.
						 */
#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
						 * VERW clears CPU fill buffer
						 * even on MDS_NO CPUs.
						 */
#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
						 * bit available to control VERW
						 * behavior.
						 */
#define ARCH_CAP_RRSBA			BIT(19)	/*
						 * Indicates RET may use predictors
						 * other than the RSB. With eIBRS
						 * enabled predictions in kernel mode
						 * are restricted to targets in
						 * kernel.
						 */
#define ARCH_CAP_BHI_NO			BIT(20)	/*
						 * CPU is not affected by Branch
						 * History Injection.
						 */
#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
						 * Not susceptible to Post-Barrier
						 * Return Stack Buffer Predictions.
						 */
#define ARCH_CAP_GDS_CTRL		BIT(25)	/*
						 * CPU is vulnerable to Gather
						 * Data Sampling (GDS) and
						 * has controls for mitigation.
						 */
#define ARCH_CAP_GDS_NO			BIT(26)	/*
						 * CPU is not vulnerable to Gather
						 * Data Sampling (GDS).
						 */
#define ARCH_CAP_RFDS_NO		BIT(27)	/*
						 * Not susceptible to Register
						 * File Data Sampling.
						 */
#define ARCH_CAP_RFDS_CLEAR		BIT(28)	/*
						 * VERW clears CPU Register
						 * File.
						 */

#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
						 * IA32_XAPIC_DISABLE_STATUS MSR