path: root/drivers/clk/clk-lmk04832.c

// SPDX-License-Identifier: GPL-2.0
/*
 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
 * Pin compatible with the LMK0482x family
 *
 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
 *
 * Copyright (c) 2020, Xiphos Systems Corp.
 *
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/gcd.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>

/* 0x000 - 0x00d System Functions */
#define LMK04832_REG_RST3W		0x000
#define LMK04832_BIT_RESET			BIT(7)
#define LMK04832_BIT_SPI_3WIRE_DIS		BIT(4)
#define LMK04832_REG_POWERDOWN		0x002
#define LMK04832_REG_ID_DEV_TYPE	0x003
#define LMK04832_REG_ID_PROD_MSB	0x004
#define LMK04832_REG_ID_PROD_LSB	0x005
#define LMK04832_REG_ID_MASKREV		0x006
#define LMK04832_REG_ID_VNDR_MSB	0x00c
#define LMK04832_REG_ID_VNDR_LSB	0x00d

/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
#define LMK04832_REG_CLKOUT_CTRL0(ch)	(0x100 + (ch >> 1) * 8)
#define LMK04832_BIT_DCLK_DIV_LSB		GENMASK(7, 0)
#define LMK04832_REG_CLKOUT_CTRL1(ch)	(0x101 + (ch >> 1) * 8)
#define LMK04832_BIT_DCLKX_Y_DDLY_LSB		GENMASK(7, 0)
#define LMK04832_REG_CLKOUT_CTRL2(ch)	(0x102 + (ch >> 1) * 8)
#define LMK04832_BIT_CLKOUTX_Y_PD		BIT(7)
#define LMK04832_BIT_DCLKX_Y_DDLY_PD		BIT(4)
#define LMK04832_BIT_DCLKX_Y_DDLY_MSB		GENMASK(3, 2)
#define LMK04832_BIT_DCLK_DIV_MSB		GENMASK(1, 0)
#define LMK04832_REG_CLKOUT_SRC_MUX(ch)	(0x103 + (ch % 2) + (ch >> 1) * 8)
#define LMK04832_BIT_CLKOUT_SRC_MUX		BIT(5)
#define LMK04832_REG_CLKOUT_CTRL3(ch)	(0x103 + (ch >> 1) * 8)
#define LMK04832_BIT_DCLKX_Y_PD			BIT(4)
#define LMK04832_BIT_DCLKX_Y_DCC		BIT(2)
#define LMK04832_BIT_DCLKX_Y_HS			BIT(0)
#define LMK04832_REG_CLKOUT_CTRL4(ch)	(0x104 + (ch >> 1) * 8)
#define LMK04832_BIT_SCLK_PD			BIT(4)
#define LMK04832_BIT_SCLKX_Y_DIS_MODE		GENMASK(3, 2)
#define LMK04832_REG_SCLKX_Y_ADLY(ch)	(0x105 + (ch >> 1) * 8)
#define LMK04832_REG_SCLKX_Y_DDLY(ch)	(0x106 + (ch >> 1) * 8)
#define LMK04832_BIT_SCLKX_Y_DDLY		GENMASK(3, 0)
#define LMK04832_REG_CLKOUT_FMT(ch)	(0x107 + (ch >> 1) * 8)
#define LMK04832_BIT_CLKOUT_FMT(ch)		(ch % 2 ? 0xf0 : 0x0f)
#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN		0x00
#define LMK04832_VAL_CLKOUT_FMT_LVDS			0x01
#define LMK04832_VAL_CLKOUT_FMT_HSDS6			0x02
#define LMK04832_VAL_CLKOUT_FMT_HSDS8			0x03
#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600		0x04
#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000		0x05
#define LMK04832_VAL_CLKOUT_FMT_LCPECL			0x06
#define LMK04832_VAL_CLKOUT_FMT_CML16			0x07
#define LMK04832_VAL_CLKOUT_FMT_CML24			0x08
#define LMK04832_VAL_CLKOUT_FMT_CML32			0x09
#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV		0x0a
#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF		0x0b
#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV		0x0c
#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR		0x0d
#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV		0x0e
#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR		0x0f

/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
#define LMK04832_REG_VCO_OSCOUT		0x138
#define LMK04832_BIT_VCO_MUX			GENMASK(6, 5)
#define LMK04832_VAL_VCO_MUX_VCO0			0x00
#define LMK04832_VAL_VCO_MUX_VCO1			0x01
#define LMK04832_VAL_VCO_MUX_EXT			0x02
#define LMK04832_REG_SYSREF_OUT		0x139
#define LMK04832_BIT_SYSREF_REQ_EN		BIT(6)
#define LMK04832_BIT_SYSREF_MUX			GENMASK(1, 0)
#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC		0x00
#define LMK04832_VAL_SYSREF_MUX_RECLK			0x01
#define LMK04832_VAL_SYSREF_MUX_PULSER			0x02
#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS		0x03
#define LMK04832_REG_SYSREF_DIV_MSB	0x13a
#define LMK04832_BIT_SYSREF_DIV_MSB		GENMASK(4, 0)
#define LMK04832_REG_SYSREF_DIV_LSB	0x13b
#define LMK04832_REG_SYSREF_DDLY_MSB	0x13c
#define LMK04832_BIT_SYSREF_DDLY_MSB		GENMASK(4, 0)
#define LMK04832_REG_SYSREF_DDLY_LSB	0x13d
#define LMK04832_REG_SYSREF_PULSE_CNT	0x13e
#define LMK04832_REG_FB_CTRL		0x13f
#define LMK04832_BIT_PLL2_RCLK_MUX		BIT(7)
#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN		0x00
#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN		0x01
#define LMK04832_BIT_PLL2_NCLK_MUX		BIT(5)
#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P		0x00
#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX		0x01
#define LMK04832_BIT_FB_MUX_EN			BIT(0)
#define LMK04832_REG_MAIN_PD		0x140
#define LMK04832_BIT_PLL1_PD			BIT(7)
#define LMK04832_BIT_VCO_LDO_PD			BIT(6)
#define LMK04832_BIT_VCO_PD			BIT(5)
#define LMK04832_BIT_OSCIN_PD			BIT(4)
#define LMK04832_BIT_SYSREF_GBL_PD		BIT(3)
#define LMK04832_BIT_SYSREF_PD			BIT(2)
#define LMK04832_BIT_SYSREF_DDLY_PD		BIT(1)
#define LMK04832_BIT_SYSREF_PLSR_PD		BIT(0)
#define LMK04832_REG_SYNC		0x143
#define LMK04832_BIT_SYNC_CLR			BIT(7)
#define LMK04832_BIT_SYNC_1SHOT_EN		BIT(6)
#define LMK04832_BIT_SYNC_POL			BIT(5)
#define LMK04832_BIT_SYNC_EN			BIT(4)
#define LMK04832_BIT_SYNC_MODE			GENMASK(1, 0)
#define LMK04832_VAL_SYNC_MODE_OFF			0x00
#define LMK04832_VAL_SYNC_MODE_ON			0x01
#define LMK04832_VAL_SYNC_MODE_PULSER_PIN		0x02
#define LMK04832_VAL_SYNC_MODE_PULSER_SPI		0x03
#define LMK04832_REG_SYNC_DIS		0x144

/* 0x146 - 0x14a CLKin Control */
#define LMK04832_REG_CLKIN_SEL0		0x148
#define LMK04832_REG_CLKIN_SEL1		0x149
#define LMK04832_REG_CLKIN_RST		0x14a
#define LMK04832_BIT_SDIO_RDBK_TYPE		BIT(6)
#define LMK04832_BIT_CLKIN_SEL_MUX		GENMASK(5, 3)
#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK		0x06
#define LMK04832_BIT_CLKIN_SEL_TYPE		GENMASK(2, 0)
#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT			0x03

/* 0x14b - 0x152 Holdover */

/* 0x153 - 0x15f PLL1 Configuration */
#define LMK04832_REG_PLL1_LD		0x15f
#define LMK04832_BIT_PLL1_LD_MUX		GENMASK(7, 3)
#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK		0x07
#define LMK04832_BIT_PLL1_LD_TYPE		GENMASK(2, 0)
#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP		0x03

/* 0x160 - 0x16e PLL2 Configuration */
#define L