path: root/drivers/clk/renesas/r9a06g032-clocks.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R9A06G032 clock driver
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/soc/renesas/r9a06g032-sysctrl.h>
#include <linux/spinlock.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

#define R9A06G032_SYSCTRL_USB    0x00
#define R9A06G032_SYSCTRL_USB_H2MODE  (1<<1)
#define R9A06G032_SYSCTRL_DMAMUX 0xA0

/**
 * struct regbit - describe one bit in a register
 * @reg: offset of register relative to base address,
 *          expressed in units of 32-bit words (not bytes),
 * @bit: which bit (0 to 31) in the register
 *
 * This structure is used to compactly encode the location
 * of a single bit in a register. Five bits are needed to
 * encode the bit number. With uint16_t data type, this
 * leaves 11 bits to encode a register offset up to 2047.
 *
 * Since registers are aligned on 32-bit boundaries, the
 * offset will be specified in 32-bit words rather than bytes.
 * This allows encoding an offset up to 0x1FFC (8188) bytes.
 *
 * Helper macro RB() takes care of converting the register
 * offset from bytes to 32-bit words.
 */
struct regbit {
	u16 bit:5;
	u16 reg:11;
};

#define RB(_reg, _bit) ((struct regbit) { \
	.reg = (_reg) / 4, \
	.bit = (_bit) \
})

/**
 * struct r9a06g032_gate - clock-related control bits
 * @gate:   clock enable/disable
 * @reset:  clock module reset (active low)
 * @ready:  enables NoC forwarding of read/write requests to device,
 *          (eg. device is ready to handle read/write requests)
 * @midle:  request to idle the NoC interconnect
 *
 * Each of these fields describes a single bit in a register,
 * which controls some aspect of clock gating. The @gate field
 * is mandatory, this one enables/disables the clock. The
 * other fields are optional, with zero indicating "not used".
 *
 * In most cases there is a @reset bit which needs to be
 * de-asserted to bring the module out of reset.
 *
 * Modules may also need to signal when they are @ready to
 * handle requests (read/writes) from the NoC interconnect.
 *
 * Similarly, the @midle bit is used to idle the master.
 */
struct r9a06g032_gate {
	struct regbit gate, reset, ready, midle;
	/* Unused fields omitted to save space */
	/* struct regbit scon, mirack, mistat */;
};

enum gate_type {
	K_GATE = 0,	/* gate which enable/disable */
	K_FFC,		/* fixed factor clock */
	K_DIV,		/* divisor */
	K_BITSEL,	/* special for UARTs */
	K_DUALGATE	/* special for UARTs */
};

/**
 * struct r9a06g032_clkdesc - describe a single clock
 * @name:      string describing this clock
 * @managed:   boolean indicating if this clock should be
 *             started/stopped as part of power management
 * @type:      see enum @gate_type
 * @index:     the ID of this clock element
 * @source:    the ID+1 of the parent clock element.
 *             Root clock uses ID of ~0 (PARENT_ID);
 * @gate:      clock enable/disable
 * @div:       substructure for clock divider
 * @div.min:   smallest permitted clock divider
 * @div.max:   largest permitted clock divider
 * @div.reg:   clock divider register offset, in 32-bit words
 * @div.table: optional list of fixed clock divider values;
 *             must be in ascending order, zero for unused
 * @ffc:       substructure for fixed-factor clocks
 * @ffc.div:   divisor for fixed-factor clock
 * @ffc.mul:   multiplier for fixed-factor clock
 * @dual:      substructure for dual clock g