path: root/drivers/crypto/hisilicon/debugfs.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2022 HiSilicon Limited. */
#include <linux/hisi_acc_qm.h>
#include "qm_common.h"

#define QM_DFX_BASE			0x0100000
#define QM_DFX_STATE1			0x0104000
#define QM_DFX_STATE2			0x01040C8
#define QM_DFX_COMMON			0x0000
#define QM_DFX_BASE_LEN			0x5A
#define QM_DFX_STATE1_LEN		0x2E
#define QM_DFX_STATE2_LEN		0x11
#define QM_DFX_COMMON_LEN		0xC3
#define QM_DFX_REGS_LEN			4UL
#define QM_DBG_TMP_BUF_LEN		22
#define QM_XQC_ADDR_MASK		GENMASK(31, 0)
#define CURRENT_FUN_MASK		GENMASK(5, 0)
#define CURRENT_Q_MASK			GENMASK(31, 16)
#define QM_SQE_ADDR_MASK		GENMASK(7, 0)

#define QM_DFX_MB_CNT_VF		0x104010
#define QM_DFX_DB_CNT_VF		0x104020
#define QM_DFX_SQE_CNT_VF_SQN		0x104030
#define QM_DFX_CQE_CNT_VF_CQN		0x104040
#define QM_DFX_QN_SHIFT			16
#define QM_DFX_CNT_CLR_CE		0x100118
#define QM_DBG_WRITE_LEN		1024
#define QM_IN_IDLE_ST_REG		0x1040e4
#define QM_IN_IDLE_STATE		0x1

static const char * const qm_debug_file_name[] = {
	[CURRENT_QM]   = "current_qm",
	[CURRENT_Q]    = "current_q",
	[CLEAR_ENABLE] = "clear_enable",
};

static const char * const qm_s[] = {
	"work", "stop",
};

struct qm_dfx_item {
	const char *name;
	u32 offset;
};

struct qm_cmd_dump_item {
	const char *cmd;
	char *info_name;
	int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
};

static struct qm_dfx_item qm_dfx_files[] = {
	{"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
	{"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
	{"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
	{"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
	{"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
};

#define CNT_CYC_REGS_NUM		10
static const struct debugfs_reg32 qm_dfx_regs[] = {
	/* XXX_CNT are reading clear register */
	{"QM_ECC_1BIT_CNT               ",  0x104000},
	{"QM_ECC_MBIT_CNT               ",  0x104008},
	{"QM_DFX_MB_CNT                 ",  0x104018},
	{"QM_DFX_DB_CNT                 ",  0x104028},
	{"QM_DFX_SQE_CNT                ",  0x104038},
	{"QM_DFX_CQE_CNT                ",  0x104048},
	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050},
	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058},
	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060},
	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4},
	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},
	{"QM_ECC_1BIT_INF               ",  0x104004},
	{"QM_ECC_MBIT_INF               ",  0x10400c},
	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0},
	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4},
	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8},
	{"QM_DFX_FF_ST0                 ",  0x1040c8},
	{"QM_DFX_FF_ST1                 ",  0x1040cc},
	{"QM_DFX_FF_ST2                 ",  0x1040d0},
	{"QM_DFX_FF_ST3                 ",  0x1040d4},
	{"QM_DFX_FF_ST4                 ",  0x1040d8},
	{"QM_DFX_FF_ST5                 ",  0x1040dc},
	{"QM_DFX_FF_ST6                 ",  0x1040e0},
	{"QM_IN_IDLE_ST                 ",  0x1040e4},
	{"QM_CACHE_CTL                  ",  0x100050},
	{"QM_TIMEOUT_CFG                ",  0x100070},
	{"QM_DB_TIMEOUT_CFG             ",  0x100074},
	{"QM_FLR_PENDING_TIME_CFG       ",  0x100078},
	{"QM_ARUSR_MCFG1                ",  0x100088},
	{"QM_AWUSR_MCFG1                ",  0x100098},
	{"QM_AXI_M_CFG_ENABLE           ",  0x1000B0},
	{"QM_RAS_CE_THRESHOLD           ",  0x1000F8},
	{"QM_AXI_TIMEOUT_CTRL           ",  0x100120},
	{"QM_AXI_TIMEOUT_STATUS         ",  0x100124},
	{"QM_CQE_AGGR_TIMEOUT_CTRL      ",  0x100144},
	{"ACC_RAS_MSI_INT_SEL           ",  0x1040fc},
	{"QM_CQE_OUT                    ",  0x104100},
	{"QM_EQE_OUT                    ",  0x104104},
	{"QM_AEQE_OUT                   ",  0x104108},
	{"QM_DB_INFO0                   ",  0x104180},
	{"QM_DB_INFO1                   ",  0x104184},
	{"QM_AM_CTRL_GLOBAL             ",  0x300000},
	{"QM_AM_CURR_PORT_STS           ",  0x300100},
	{"QM_AM_CURR_TRANS_RETURN       ",  0x300150},
	{"QM_AM_CURR_RD_MAX_TXID        ",  0x300154},
	{"QM_AM_CURR_WR_MAX_TXID        ",  0x300158},
	{"QM_AM_ALARM_RRESP             ",  0x300180},
	{"QM_AM_ALARM_BRESP             ",  0x300184},
};

static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},
};