// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2022 HiSilicon Limited. */
#include <linux/hisi_acc_qm.h>
#include "qm_common.h"
#define QM_DFX_BASE 0x0100000
#define QM_DFX_STATE1 0x0104000
#define QM_DFX_STATE2 0x01040C8
#define QM_DFX_COMMON 0x0000
#define QM_DFX_BASE_LEN 0x5A
#define QM_DFX_STATE1_LEN 0x2E
#define QM_DFX_STATE2_LEN 0x11
#define QM_DFX_COMMON_LEN 0xC3
#define QM_DFX_REGS_LEN 4UL
#define QM_DBG_TMP_BUF_LEN 22
#define CURRENT_FUN_MASK GENMASK(5, 0)
#define CURRENT_Q_MASK GENMASK(31, 16)
#define QM_SQE_ADDR_MASK GENMASK(7, 0)
#define QM_DFX_MB_CNT_VF 0x104010
#define QM_DFX_DB_CNT_VF 0x104020
#define QM_DFX_SQE_CNT_VF_SQN 0x104030
#define QM_DFX_CQE_CNT_VF_CQN 0x104040
#define QM_DFX_QN_SHIFT 16
#define QM_DFX_CNT_CLR_CE 0x100118
#define QM_DBG_WRITE_LEN 1024
static const char * const qm_debug_file_name[] = {
[CURRENT_QM] = "current_qm",
[CURRENT_Q] = "current_q",
[CLEAR_ENABLE] = "clear_enable",
};
static const char * const qm_s[] = {
"work", "stop",
};
struct qm_dfx_item {
const char *name;
u32 offset;
};
struct qm_cmd_dump_item {
const char *cmd;
char *info_name;
int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
};
static struct qm_dfx_item qm_dfx_files[] = {
{"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
{"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
{"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
{"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
{"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
};
#define CNT_CYC_REGS_NUM 10
static const struct debugfs_reg32 qm_dfx_regs[] = {
/* XXX_CNT are reading clear register */
{"QM_ECC_1BIT_CNT ", 0x104000},
{"QM_ECC_MBIT_CNT ", 0x104008},
{"QM_DFX_MB_CNT ", 0x104018},
{"QM_DFX_DB_CNT ", 0x104028},
{"QM_DFX_SQE_CNT ", 0x104038},
{"QM_DFX_CQE_CNT ", 0x104048},
{"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050},
{"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058},
{"QM_DFX_ACC_FINISH_CNT ", 0x104060},
{"QM_DFX_CQE_ERR_CNT ", 0x1040b4},
{"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
{"QM_ECC_1BIT_INF ", 0x104004},
{"QM_ECC_MBIT_INF ", 0x10400c},
{"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0},
{"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4},
{"QM_DFX_AXI_RDY_VLD ", 0x1040a8},
{"QM_DFX_FF_ST0 ", 0x1040c8},
{"QM_DFX_FF_ST1 ", 0x1040cc},
{"QM_DFX_FF_ST2 ", 0x1040d0},
{"QM_DFX_FF_ST3 ", 0x1040d4},
{"QM_DFX_FF_ST4 ", 0x1040d8},
{"QM_DFX_FF_ST5 ", 0x1040dc},
{"QM_DFX_FF_ST6 ", 0x1040e0},
{"QM_IN_IDLE_ST ", 0x1040e4},
};
static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
{"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
};
/* define the QM's dfx regs region and region length */
static struct dfx_diff_registers qm_diff_regs[] = {
{
.reg_offset = QM_DFX_BASE,
.reg_len = QM_DFX_BASE_LEN,
}, {
.reg_offset = QM_DFX_STATE1,
.reg_len = QM_DFX_STATE1_LEN,
}, {
.reg_offset = QM_DFX_STATE2,
.reg_len = QM_DFX_STATE2_LEN,
}, {
.reg_offset = QM_DFX_COMMON,
.reg_len = QM_DFX_COMMON_LEN,
},
};
static struct hisi_qm *file_to_qm(struct debugfs_file *file)
{
struct qm_debug *debug = file->debug;
return container_of(debug, struct hisi_qm, debug);
}
static ssize_t qm_cmd_read(struct file *filp, char __user *buffer,
size_t count, loff_t *pos)
{
char buf[QM_DBG_READ_LEN];
int len;
len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n",
"Please echo help to cmd to get help information");
return simple_read_from_buffer(buffer, count, pos, buf, len);
}
static void dump_show(struct hisi_qm *qm, void *info,
unsigned int info_size, char *info_name)
{
struct device *dev = &qm->pdev->dev;
u8 *info_curr = info;
u32 i;
#define BYTE_PER_DW 4
dev_info(dev, "%s DUMP\n", info_name);
for (i = 0; i < info_size; i += BYTE_PER_DW, info_curr += BYTE_PER_DW) {
pr_info("DW%u: %02X%02X %02X%02X\n", i / BYTE_PER_DW,
*(info_curr + 3), *(info_curr + 2), *(info