path: root/drivers/crypto/hisilicon/sec2/sec_main.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 HiSilicon Limited. */

#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/topology.h>
#include <linux/uacce.h>

#include "sec.h"

#define SEC_VF_NUM			63
#define SEC_QUEUE_NUM_V1		4096
#define PCI_DEVICE_ID_HUAWEI_SEC_PF	0xa255

#define SEC_BD_ERR_CHK_EN0		0xEFFFFFFF
#define SEC_BD_ERR_CHK_EN1		0x7ffff7fd
#define SEC_BD_ERR_CHK_EN3		0xffffbfff

#define SEC_SQE_SIZE			128
#define SEC_PF_DEF_Q_NUM		256
#define SEC_PF_DEF_Q_BASE		0
#define SEC_CTX_Q_NUM_DEF		2
#define SEC_CTX_Q_NUM_MAX		32

#define SEC_CTRL_CNT_CLR_CE		0x301120
#define SEC_CTRL_CNT_CLR_CE_BIT	BIT(0)
#define SEC_CORE_INT_SOURCE		0x301010
#define SEC_CORE_INT_MASK		0x301000
#define SEC_CORE_INT_STATUS		0x301008
#define SEC_CORE_SRAM_ECC_ERR_INFO	0x301C14
#define SEC_ECC_NUM			16
#define SEC_ECC_MASH			0xFF
#define SEC_CORE_INT_DISABLE		0x0

#define SEC_RAS_CE_REG			0x301050
#define SEC_RAS_FE_REG			0x301054
#define SEC_RAS_NFE_REG			0x301058
#define SEC_RAS_FE_ENB_MSK		0x0
#define SEC_OOO_SHUTDOWN_SEL		0x301014
#define SEC_RAS_DISABLE		0x0
#define SEC_MEM_START_INIT_REG	0x301100
#define SEC_MEM_INIT_DONE_REG		0x301104

/* clock gating */
#define SEC_CONTROL_REG		0x301200
#define SEC_DYNAMIC_GATE_REG		0x30121c
#define SEC_CORE_AUTO_GATE		0x30212c
#define SEC_DYNAMIC_GATE_EN		0x7fff
#define SEC_CORE_AUTO_GATE_EN		GENMASK(3, 0)
#define SEC_CLK_GATE_ENABLE		BIT(3)
#define SEC_CLK_GATE_DISABLE		(~BIT(3))

#define SEC_TRNG_EN_SHIFT		8
#define SEC_AXI_SHUTDOWN_ENABLE	BIT(12)
#define SEC_AXI_SHUTDOWN_DISABLE	0xFFFFEFFF

#define SEC_INTERFACE_USER_CTRL0_REG	0x301220
#define SEC_INTERFACE_USER_CTRL1_REG	0x301224
#define SEC_SAA_EN_REG			0x301270
#define SEC_BD_ERR_CHK_EN_REG0		0x301380
#define SEC_BD_ERR_CHK_EN_REG1		0x301384
#define SEC_BD_ERR_CHK_EN_REG3		0x30138c

#define SEC_USER0_SMMU_NORMAL		(BIT(23) | BIT(15))
#define SEC_USER1_SMMU_NORMAL		(BIT(31) | BIT(23) | BIT(15) | BIT(7))
#define SEC_USER1_ENABLE_CONTEXT_SSV	BIT(24)
#define SEC_USER1_ENABLE_DATA_SSV	BIT(16)
#define SEC_USER1_WB_CONTEXT_SSV	BIT(8)
#define SEC_USER1_WB_DATA_SSV		BIT(0)
#define SEC_USER1_SVA_SET		(SEC_USER1_ENABLE_CONTEXT_SSV | \
					SEC_USER1_ENABLE_DATA_SSV | \
					SEC_USER1_WB_CONTEXT_SSV |  \
					SEC_USER1_WB_DATA_SSV)
#define SEC_USER1_SMMU_SVA		(SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
#define SEC_USER1_SMMU_MASK		(~SEC_USER1_SVA_SET)
#define SEC_INTERFACE_USER_CTRL0_REG_V3	0x302220
#define SEC_INTERFACE_USER_CTRL1_REG_V3	0x302224
#define SEC_USER1_SMMU_NORMAL_V3	(BIT(23) | BIT(17) | BIT(11) | BIT(5))
#define SEC_USER1_SMMU_MASK_V3		0xFF79E79E
#define SEC_CORE_INT_STATUS_M_ECC	BIT(2)

#define SEC_PREFETCH_CFG		0x301130
#define SEC_SVA_TRANS			0x301EC4
#define SEC_PREFETCH_ENABLE		(~(BIT(0) | BIT(1) | BIT(11)))
#define SEC_PREFETCH_DISABLE		BIT(1)
#define SEC_SVA_DISABLE_READY		(BIT(7) | BIT(11))

#define SEC_DELAY_10_US			10
#define SEC_POLL_TIMEOUT_US		1000
#define SEC_DBGFS_VAL_MAX_LEN		20
#define SEC_SINGLE_PORT_MAX_TRANS	0x2060

#define SEC_SQE_MASK_OFFSET		64
#define SEC_SQE_MASK_LEN		48
#define SEC_SHAPER_TYPE_RATE		400

#define SEC_DFX_BASE		0x301000
#define SEC_DFX_CORE		0x302100
#define SEC_DFX_COMMON1		0x301600
#define SEC_DFX_COMMON2		0x301C00
#define SEC_DFX_BASE_LEN		0x9D
#define SEC_DFX_CORE_LEN		0x32B
#define SEC_DFX_COMMON1_LEN		0x45
#define SEC_DFX_COMMON2_LEN		0xBA

#define SEC_ALG_BITMAP_SHIFT		32

#define SEC_CIPHER_BITMAP		(GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
					GENMASK(24, 21))
#define SEC_DIGEST_BITMAP		(GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \
					GENMASK_ULL(42, 25))
#define SEC_AEAD_BITMAP			(GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
					GENMASK_ULL(45, 43))

struct sec_hw_error {
	u32 int_msk;
	const char *msg;
};

struct sec_dfx_item {
	const char *name;
	u32 offset;
};

static const char sec_name[] = "hisi_sec2";
static struct dentry *sec_debugfs_root;

static struct hisi_qm_list sec_devices = {
	.register_to_cry