path: root/drivers/dma/owl-dma.c

// SPDX-License-Identifier: GPL-2.0+
//
// Actions Semi Owl SoCs DMA driver
//
// Copyright (c) 2014 Actions Semi Inc.
// Author: David Liu <liuwei@actions-semi.com>
//
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_dma.h>
#include <linux/slab.h>
#include "virt-dma.h"

#define OWL_DMA_FRAME_MAX_LENGTH		0xfffff

/* Global DMA Controller Registers */
#define OWL_DMA_IRQ_PD0				0x00
#define OWL_DMA_IRQ_PD1				0x04
#define OWL_DMA_IRQ_PD2				0x08
#define OWL_DMA_IRQ_PD3				0x0C
#define OWL_DMA_IRQ_EN0				0x10
#define OWL_DMA_IRQ_EN1				0x14
#define OWL_DMA_IRQ_EN2				0x18
#define OWL_DMA_IRQ_EN3				0x1C
#define OWL_DMA_SECURE_ACCESS_CTL		0x20
#define OWL_DMA_NIC_QOS				0x24
#define OWL_DMA_DBGSEL				0x28
#define OWL_DMA_IDLE_STAT			0x2C

/* Channel Registers */
#define OWL_DMA_CHAN_BASE(i)			(0x100 + (i) * 0x100)
#define OWL_DMAX_MODE				0x00
#define OWL_DMAX_SOURCE				0x04
#define OWL_DMAX_DESTINATION			0x08
#define OWL_DMAX_FRAME_LEN			0x0C
#define OWL_DMAX_FRAME_CNT			0x10
#define OWL_DMAX_REMAIN_FRAME_CNT		0x14
#define OWL_DMAX_REMAIN_CNT			0x18
#define OWL_DMAX_SOURCE_STRIDE			0x1C
#define OWL_DMAX_DESTINATION_STRIDE		0x20
#define OWL_DMAX_START				0x24
#define OWL_DMAX_PAUSE				0x28
#define OWL_DMAX_CHAINED_CTL			0x2C
#define OWL_DMAX_CONSTANT			0x30
#define OWL_DMAX_LINKLIST_CTL			0x34
#define OWL_DMAX_NEXT_DESCRIPTOR		0x38
#define OWL_DMAX_CURRENT_DESCRIPTOR_NUM		0x3C
#define OWL_DMAX_INT_CTL			0x40
#define OWL_DMAX_INT_STATUS			0x44
#define OWL_DMAX_CURRENT_SOURCE_POINTER		0x48
#define OWL_DMAX_CURRENT_DESTINATION_POINTER	0x4C

/* OWL_DMAX_MODE Bits */
#define OWL_DMA_MODE_TS(x)			(((x) & GENMASK(5, 0)) << 0)
#define OWL_DMA_MODE_ST(x)			(((x) & GENMASK(1, 0)) << 8)
#define	OWL_DMA_MODE_ST_DEV			OWL_DMA_MODE_ST(0)
#define	OWL_DMA_MODE_ST_DCU			OWL_DMA_MODE_ST(2)
#define	OWL_DMA_MODE_ST_SRAM			OWL_DMA_MODE_ST(3)
#define OWL_DMA_MODE_DT(x)			(((x) & GENMASK(1, 0)) << 10)
#define	OWL_DMA_MODE_DT_DEV			OWL_DMA_MODE_DT(0)
#define	OWL_DMA_MODE_DT_DCU			OWL_DMA_MODE_DT(2)
#define	OWL_DMA_MODE_DT_SRAM			OWL_DMA_MODE_DT(3)
#define OWL_DMA_MODE_SAM(x)			(((x) & GENMASK(1, 0)) << 16)
#define	OWL_DMA_MODE_SAM_CONST			OWL_DMA_MODE_SAM(0)
#define	OWL_DMA_MODE_SAM_INC			OWL_DMA_MODE_SAM(1)
#define	OWL_DMA_MODE_SAM_STRIDE			OWL_DMA_MODE_SAM(2)
#define OWL_DMA_MODE_DAM(x)			(((x) & GENMASK(1, 0)) << 18)
#define	OWL_DMA_MODE_DAM_CONST			OWL_DMA_MODE_DAM(0)
#define	OWL_DMA_MODE_DAM_INC			OWL_DMA_MODE_DAM(1)
#define	OWL_DMA_MODE_DAM_STRIDE			OWL_DMA_MODE_DAM(2)
#define OWL_DMA_MODE_PW(x)			(((x) & GENMASK(2, 0)) << 20)
#define OWL_DMA_MODE_CB				BIT(23)
#define OWL_DMA_MODE_NDDBW(x)			(((x) & 0x1) << 28)
#define	OWL_DMA_MODE_NDDBW_32BIT		OWL_DMA_MODE_NDDBW(0)
#define	OWL_DMA_MODE_NDDBW_8BIT			OWL_DMA_MODE_NDDBW(1)
#define OWL_DMA_MODE_CFE			BIT(29)
#define OWL_DMA_MODE_LME			BIT(30)
#define OWL_DMA_MODE_CME			BIT(31)

/* OWL_DMAX_LINKLIST_CTL Bits */
#define OWL_DMA_LLC_SAV(x)			(((x) & GENMASK(1, 0)) << 8)
#define	OWL_DMA_LLC_SAV_INC			OWL_DMA_LLC_SAV(0)
#define	OWL_DMA_LLC_SAV_LOAD_NEXT		OWL_DMA_LLC_SAV(1)
#define	OWL_DMA_LLC_SAV_LOAD_PREV		OWL_DMA_LLC_SAV(2)
#define OWL_DMA_LLC_DAV(x)			(((x) & GENMASK(1, 0)) << 10)
#define	OWL_DMA_LLC_DAV_INC			OWL_DMA_LLC_DAV(0)
#define	OWL_DMA_LLC_DAV_LOAD_NEXT		OWL_DMA_LLC_DAV(1)
#define	OWL_DMA_LLC_DAV_LOAD_PREV		OWL_DMA_LLC_DAV(2)
#define OWL_DMA_LLC_SUSPEND			BIT(16)

/* OWL_DMAX_INT_CTL Bits */
#define OWL_DMA_INTCTL_BLOCK			BIT(0)
#define OWL_DMA_INTCTL_SUPER_BLOCK		BIT(1)
#define OWL_DMA_INTCTL_FRAME			BIT(2)
#define OWL_DMA_INTCTL_HALF_FRAME		BIT(3)
#define OWL_DMA_INTCTL_LAST_FRAME		BIT(4)

/* OWL_DMAX_INT_STATUS Bits */
#define OWL_DMA_INTSTAT_BLOCK			BIT(0)
#define OWL_DMA_INTSTAT_SUPER_BLOCK		BIT(1)
#define OWL_DMA_INTSTAT_FRAME			BIT(2)
#define OWL_DMA_INTSTAT_HALF_FRAME		BIT(3)
#define OWL_DMA_INTSTAT_LAST_FRAME		BIT(4)

/* Pack shift and newshift in a single word */
#define BIT_FIELD(val, width, shift, newshift)	\
		((((val) >> (shift)) & ((BIT(width)) - 1)) << (newshift))

/* Frame count value is fixed as 1 */
#define FCNT_VAL				0x1

/**
 * enum owl_dmadesc_offsets - Describe DMA descriptor, hardware link
 * list for dma transfer
 * @OWL_DMADESC_NEXT_LLI: physical address of the next link list
 * @OWL_DMADESC_SADDR: source physical address
 * @OWL_DMADESC_DADDR: destination physical address
 * @OWL_DMADESC_FLEN: frame length
 * @OWL_DMADESC_SRC_STRIDE: source stride
 * @OWL_DMADESC_DST_STRIDE: destination stride
 * @OWL_DMADESC_CTRLA: dma_mode and linklist ctrl config
 * @OWL_DMADESC_CTRLB: interrupt config
 * @OWL_DMADESC_CONST_NUM: data for constant fill
 * @OWL_DMADESC_SIZE: max size of this enum
 */
enum owl_dmadesc_offsets {
	OWL_DMADESC_NEXT_LLI = 0,
	OWL_DMADESC_SADDR,
	OWL_DMADESC_DADDR,
	OWL_DMADESC_FLEN,
	OWL_DMADESC_SRC_STRIDE,
	OWL_DMADESC_DST_STRIDE,
	OWL_DMADESC_CTRLA,
	OWL_DMADESC_CTRLB,
	OWL_DMADESC_CONST_NUM,
	OWL_DMADESC_SIZE
};

enum owl_dma_id {
	S900_DMA,
	S700_DMA,
};

/**
 * struct owl_dma_lli - Link list for dma transfer
 * @hw: hardware link list
 * @phys: physical address of hardware link list
 * @node: node for txd's lli_list
 */
struct owl_dma_lli {
	u32			hw[OWL_DMADESC_SIZE];
	dma_addr_t		phys;
	struct list_head	node;
};

/**
 * struct owl_dma_txd - Wrapper for struct dma_async_tx_descriptor
 * @vd: virtual DMA descriptor
 * @lli_list: link list of lli nodes
 * @cyclic: flag to indicate cyclic transfers
 */
struct owl_dma_txd {
	struct virt_dma_desc	vd;
	struct list_head	lli_list;
	bool			cyclic;
};

/**
 * struct owl_dma_pchan - Holder for the physical channels
 * @id: physical index to this channel
 * @base: virtual memory base for the dma channel
 * @vchan: the virtual channel currently being served by this physical channel
 */
struct owl_dma_pchan {
	u32			id;
	void __iomem		*base;
	struct owl_dma_vchan	*vchan;