path: root/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include <linux/module.h>
#include "amdgpu.h"
#include "soc15_common.h"
#include "soc21.h"
#include "gc/gc_12_0_0_offset.h"
#include "gc/gc_12_0_0_sh_mask.h"
#include "gc/gc_11_0_0_default.h"
#include "v12_structs.h"
#include "mes_v12_api_def.h"

MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");

static int mes_v12_0_hw_init(void *handle);
static int mes_v12_0_hw_fini(void *handle);
static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);

#define MES_EOP_SIZE   2048

static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring->use_doorbell) {
		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
			     ring->wptr);
		WDOORBELL64(ring->doorbell_index, ring->wptr);
	} else {
		BUG();
	}
}

static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
{
	return *ring->rptr_cpu_addr;
}

static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
{
	u64 wptr;

	if (ring->use_doorbell)
		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
	else
		BUG();
	return wptr;
}

static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
	.type = AMDGPU_RING_TYPE_MES,
	.align_mask = 1,
	.nop = 0,
	.support_64bit_ptrs = true,
	.get_rptr = mes_v12_0_ring_get_rptr,
	.get_wptr = mes_v12_0_ring_get_wptr,
	.set_wptr = mes_v12_0_ring_set_wptr,
	.insert_nop = amdgpu_ring_insert_nop,
};

static const char *mes_v12_0_opcodes[] = {
	"SET_HW_RSRC",
	"SET_SCHEDULING_CONFIG",
	"ADD_QUEUE",
	"REMOVE_QUEUE",
	"PERFORM_YIELD",
	"SET_GANG_PRIORITY_LEVEL",
	"SUSPEND",
	"RESUME",
	"RESET",
	"SET_LOG_BUFFER",
	"CHANGE_GANG_PRORITY",
	"QUERY_SCHEDULER_STATUS",
	"unused",
	"SET_DEBUG_VMID",
	"MISC",
	"UPDATE_ROOT_PAGE_TABLE",
	"AMD_LOG",
	"SET_SE_MODE",
	"SET_GANG_SUBMIT",
	"SET_HW_RSRC_1",
};

static const char *mes_v12_0_misc_opcodes[] = {
	"WRITE_REG",
	"INV_GART",
	"QUERY_STATUS",
	"READ_REG",
	"WAIT_REG_MEM",
	"SET_SHADER_DEBUGGER",
	"NOTIFY_WORK_ON_UNMAPPED_QUEUE",
	"NOTIFY_TO_UNMAP_PROCESSES",
};

static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
{
	const char *op_str = NULL;

	if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
		op_str = mes_v12_0_opcodes[x_pkt->header.opcode];

	return op_str;
}

static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
{
	const char *op_str = NULL;

	if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
	    (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
		op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];

	return op_str;
}

static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
					    int pipe, void *pkt, int size,
					    int api_status_off)
{
	union MESAPI__QUERY_MES_STATUS mes_status_pkt;
	signed long timeout = 3000000; /* 3000 ms */
	struct amdgpu_device *adev = mes->adev;
	struct amdgpu_ring *ring = &mes->ring[pipe];
	spinlock_t *ring_lock = &mes->ring_lock[pipe];
	struct MES_API_STATUS *api_status;
	union MESAPI__MISC *x_pkt = pkt;
	const char *op_str, *misc_op_str;
	unsigned long flags;
	u64 status_gpu_addr;
	u32 seq, status_offset;
	u64 *status_ptr;
	signed long r;
	int ret;

	if (x_pkt->header.opcode >= MES_SCH_API_MAX)
		return -EINVAL;

	if (amdgpu_emu_mode) {
		timeout *= 100;
	} else if (amdgpu_sriov_vf(adev)) {
		/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
		timeout = 15 *