/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_vcn.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
#include "vcn/vcn_5_0_0_offset.h"
#include "vcn/vcn_5_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
#include "vcn_v5_0_0.h"
#include <drm/drm_drv.h>
static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = {
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
SOC15_REG_ENTRY_STR(VCN, 0