path: root/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

/*
 * Copyright 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

/**
 * Bandwidth and Watermark calculations interface.
 * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
 */
#ifndef __DCN_CALCS_H__
#define __DCN_CALCS_H__

#include "bw_fixed.h"
#include "../dml/display_mode_lib.h"
#include "hw/clk_mgr.h"

struct dc;
struct dc_state;

/*******************************************************************************
 * DCN data structures.
 ******************************************************************************/

#define number_of_planes   6
#define number_of_planes_minus_one   5
#define number_of_states   4
#define number_of_states_plus_one   5

#define ddr4_dram_width   64
#define ddr4_dram_factor_single_Channel   16
enum dcn_bw_defs {
	dcn_bw_v_min0p65,
	dcn_bw_v_mid0p72,
	dcn_bw_v_nom0p8,
	dcn_bw_v_max0p9,
	dcn_bw_v_max0p91,
	dcn_bw_no_support = 5,
	dcn_bw_yes,
	dcn_bw_hor,
	dcn_bw_vert,
	dcn_bw_override,
	dcn_bw_rgb_sub_64,
	dcn_bw_rgb_sub_32,
	dcn_bw_rgb_sub_16,
	dcn_bw_no,
	dcn_bw_sw_linear,
	dcn_bw_sw_4_kb_d,
	dcn_bw_sw_4_kb_d_x,
	dcn_bw_sw_64_kb_d,
	dcn_bw_sw_64_kb_d_t,
	dcn_bw_sw_64_kb_d_x,
	dcn_bw_sw_var_d,
	dcn_bw_sw_var_d_x,
	dcn_bw_yuv420_sub_8,
	dcn_bw_sw_4_kb_s,
	dcn_bw_sw_4_kb_s_x,
	dcn_bw_sw_64_kb_s,
	dcn_bw_sw_64_kb_s_t,
	dcn_bw_sw_64_kb_s_x,
	dcn_bw_writeback,
	dcn_bw_444,
	dcn_bw_dp,
	dcn_bw_420,
	dcn_bw_hdmi,
	dcn_bw_sw_var_s,
	dcn_bw_sw_var_s_x,
	dcn_bw_yuv420_sub_10,
	dcn_bw_supported_in_v_active,
	dcn_bw_supported_in_v_blank,
	dcn_bw_not_supported,
	dcn_bw_na,
	dcn_bw_encoder_8bpc,
	dcn_bw_encoder_10bpc,
	dcn_bw_encoder_12bpc,
	dcn_bw_encoder_16bpc,
};

/*bounding box parameters*/
/*mode parameters*/
/*system configuration*/
/* display configuration*/
struct dcn_bw_internal_vars {
	float voltage[number_of_states_plus_one + 1];
	float max_dispclk[number_of_states_plus_one + 1];
	float max_dppclk[number_of_states_plus_one + 1];
	float dcfclk_per_state[number_of_states_plus_one + 1];
	float phyclk_per_state[number_of_states_plus_one + 1];
	float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
	float sr_exit_time;
	float sr_enter_plus_exit_time;
	float dram_clock_change_latency;
	float urgent_latency;
	float write_back_latency;
	float percent_of_ideal_drambw_received_after_urg_latency;
	float dcfclkv_max0p9;
	float dcfclkv_nom0p8;
	float dcfclkv_mid0p72;
	float dcfclkv_min0p65;
	float max_dispclk_vmax0p9;
	float max_dppclk_vmax0p9;
	float max_dispclk_vnom0p8;
	float max_dppclk_vnom0p8;
	float max_dispclk_vmid0p72;
	float max_dppclk_vmid0p72;
	float max_dispclk_vmin0p65;
	float max_dppclk_vmin0p65;
	float socclk;
	float fabric_and_dram_bandwidth_vmax0p9;
	float fabric_and_dram_bandwidth_vnom0p8;
	float fabric_and_dram_bandwidth_vmid0p72;
	float fabric_and_dram_bandwidth_vmin0p65;
	float round_trip_ping_latency_cycles;
	float urgent_out_of_order_return_per_channel;
	float number_of_channels;
	float vmm_page_size;
	float return_bus_width;
	float rob_buffer_size_in_kbyte;
	float det_buffer_size_in_kbyte;
	float dpp_output_buffer_pixels;
	float opp_output_buffer_lines;
	float pixel_chunk_size_in_kbyte;
	float pte_chunk_size;
	float meta_chunk_size;
	float writeback_chunk_size;
	enum dcn_bw_defs odm_capability;
	enum dcn_bw_defs dsc_capability;
	float line_buffer_size;
	enum dcn_bw_defs is_line_buffer_bpp_fixed;
	float line_buffer_fixed_bpp;
	float max_line_buffer_lines;
	float writeback_luma_buffer_size;
	float writeback_chroma_buffer_size;
	float max_num_dpp;
	float max_num_writeback;
	float max_dchub_topscl_throughput;
	float max_pscl_tolb_throughput;
	float max_lb_tovscl_throughput;
	float max_vscl_tohscl_throughput;
	float max_hscl_ratio;
	float max_vscl_ratio;
	float max_hscl_taps;
	float max_vscl_taps;
	float under_scan_factor;
	float phyclkv_max0p9;
	float phyclkv_nom0p8;
	float phyclkv_mid0p72;
	float phyclkv_min0p65;
	float pte_buffer_size_in_requests;
	float dispclk_ramping_margin;
	float downspreading;
	float max_inter_dcn_tile_repeaters;
	enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
	enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
	int mode;
	float viewport_width[number_of_planes_minus_one + 1];
	float htotal[number_of_planes_minus_one + 1];
	float vtotal[number_of_planes_minus_one + 1];
	float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
	float vactive[number_of_planes_minus_one + 1];
	float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
	float viewport_height[number_of_planes_minus_one + 1];
	enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
	float dcc_rate[number_of_planes_minus_one + 1];
	enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
	float lb_bit_per_pixel[number_of_planes_minus_one + 1];
	enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
	enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
	enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
	enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
	enum dcn_bw_defs output[number_of_planes_minus_one + 1];
	float scaler_rec_out_width[number_of_planes_minus_one + 1];
	float scaler_recout_height[number_of_planes_minus_one + 1];
	float underscan_output[number_of_planes_minus_one + 1];
	float interlace_output[number_of_planes_minus_one + 1];
	float override_hta_ps[number_of_planes_minus_one + 1];
	float override_vta_ps[number_of_planes_minus_one + 1];
	float override_hta_pschroma[number_of_planes_minus_one + 1];
	float override_vta_pschroma[number_of_planes_minus_one + 1];
	float urgent_latency_support_us[number_of_planes_minus_one + 1];
	float h_ratio[number_of_planes_minus_one + 1];
	float v_ratio[number_of_planes_minus_one + 1];
	float htaps[number_of_planes_minus_one + 1];
	float vtaps[number_of_planes_minus_one + 1];
	float hta_pschroma[number_of_planes_minus_one + 1];
	float vta_pschroma[number_of_planes_minus_one + 1];
	enum dcn_bw_defs pte_enable;
	enum dcn_bw_defs synchronized_vblank;
	enum dcn_bw_defs ta_pscalculation;
	int voltage_override_level;
	int number_of_active_planes;
	int voltage_level;
	enum dcn_bw_defs immediate_flip_supported;
	float dcfclk;
	float max_phyclk;
	float fabric_and_dram_bandwidth;
	float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
	enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1];
	float required_dispclk_per_ratio[1 + 1];
	enum dcn_bw_defs error_message[1 + 1];
	int dispclk_dppclk_ratio;
	float dpp_per_plane[number_of_planes_minus_one + 1];
	float det_buffer_size_y[number_of_planes_minus_one + 1];
	float det_buffer_size_c[number_of_planes_minus_one + 1];
	float swath_height_y[number_of_planes_minus_one + 1];
	float swath_height_c[number_of_planes_minus_one + 1];
	enum dcn_bw_defs final_error_message;
	float frequency;
	float header_line;
	float header;
	enum dcn_bw_defs voltage_override;
	enum dcn_bw_defs allow_different_hratio_vratio;
	float acceptable_quality_hta_ps;
	float acceptable_quality_vta_ps;
	float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
	enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
	float required_dispclk[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1];
	float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1];
	float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1];
	enum dcn_bw_defs