path: root/drivers/gpu/drm/amd/include/v12_structs.h

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef V12_STRUCTS_H_
#define V12_STRUCTS_H_

struct v12_gfx_mqd {
    uint32_t shadow_base_lo; // offset: 0  (0x0)
    uint32_t shadow_base_hi; // offset: 1  (0x1)
    uint32_t reserved_2; // offset: 2  (0x2)
    uint32_t reserved_3; // offset: 3  (0x3)
    uint32_t fw_work_area_base_lo; // offset: 4  (0x4)
    uint32_t fw_work_area_base_hi; // offset: 5  (0x5)
    uint32_t shadow_initialized; // offset: 6  (0x6)
    uint32_t ib_vmid; // offset: 7  (0x7)
    uint32_t reserved_8; // offset: 8  (0x8)
    uint32_t reserved_9; // offset: 9  (0x9)
    uint32_t reserved_10; // offset: 10  (0xA)
    uint32_t reserved_11; // offset: 11  (0xB)
    uint32_t reserved_12; // offset: 12  (0xC)
    uint32_t reserved_13; // offset: 13  (0xD)
    uint32_t reserved_14; // offset: 14  (0xE)
    uint32_t reserved_15; // offset: 15  (0xF)
    uint32_t reserved_16; // offset: 16  (0x10)
    uint32_t reserved_17; // offset: 17  (0x11)
    uint32_t reserved_18; // offset: 18  (0x12)
    uint32_t reserved_19; // offset: 19  (0x13)
    uint32_t reserved_20; // offset: 20  (0x14)
    uint32_t reserved_21; // offset: 21  (0x15)
    uint32_t reserved_22; // offset: 22  (0x16)
    uint32_t reserved_23; // offset: 23  (0x17)
    uint32_t reserved_24; // offset: 24  (0x18)
    uint32_t reserved_25; // offset: 25  (0x19)
    uint32_t reserved_26; // offset: 26  (0x1A)
    uint32_t reserved_27; // offset: 27  (0x1B)
    uint32_t reserved_28; // offset: 28  (0x1C)
    uint32_t reserved_29; // offset: 29  (0x1D)
    uint32_t reserved_30; // offset: 30  (0x1E)
    uint32_t reserved_31; // offset: 31  (0x1F)
    uint32_t reserved_32; // offset: 32  (0x20)
    uint32_t reserved_33; // offset: 33  (0x21)
    uint32_t reserved_34; // offset: 34  (0x22)
    uint32_t reserved_35; // offset: 35  (0x23)
    uint32_t reserved_36; // offset: 36  (0x24)
    uint32_t reserved_37; // offset: 37  (0x25)
    uint32_t reserved_38; // offset: 38  (0x26)
    uint32_t reserved_39; // offset: 39  (0x27)
    uint32_t reserved_40; // offset: 40  (0x28)
    uint32_t reserved_41; // offset: 41  (0x29)
    uint32_t reserved_42; // offset: 42  (0x2A)
    uint32_t reserved_43; // offset: 43  (0x2B)
    uint32_t reserved_44; // offset: 44  (0x2C)
    uint32_t reserved_45; // offset: 45  (0x2D)
    uint32_t reserved_46; // offset: 46  (0x2E)
    uint32_t reserved_47; // offset: 47  (0x2F)
    uint32_t reserved_48; // offset: 48  (0x30)
    uint32_t reserved_49; // offset: 49  (0x31)
    uint32_t reserved_50; // offset: 50  (0x32)
    uint32_t reserved_51; // offset: 51  (0x33)
    uint32_t reserved_52; // offset: 52  (0x34)
    uint32_t reserved_53; // offset: 53  (0x35)
    uint32_t reserved_54; // offset: 54  (0x36)
    uint32_t reserved_55; // offset: 55  (0x37)
    uint32_t reserved_56; // offset: 56  (0x38)
    uint32_t reserved_57; // offset: 57  (0x39)
    uint32_t reserved_58; // offset: 58  (0x3A)
    uint32_t reserved_59; // offset: 59  (0x3B)
    uint32_t reserved_60; // offset: 60  (0x3C)
    uint32_t reserved_61; // offset: 61  (0x3D)
    uint32_t reserved_62; // offset: 62  (0x3E)
    uint32_t reserved_63; // offset: 63  (0x3F)
    uint32_t reserved_64; // offset: 64  (0x40)
    uint32_t reserved_65; // offset: 65  (0x41)
    uint32_t reserved_66; // offset: 66  (0x42)
    uint32_t reserved_67; // offset: 67  (0x43)
    uint32_t reserved_68; // offset: 68  (0x44)
    uint32_t reserved_69; // offset: 69  (0x45)
    uint32_t reserved_70; // offset: 70  (0x46)
    uint32_t reserved_71; // offset: 71  (0x47)
    uint32_t reserved_72; // offset: 72  (0x48)
    uint32_t reserved_73; // offset: 73  (0x49)
    uint32_t reserved_74; // offset: 74  (0x4A)
    uint32_t reserved_75; // offset: 75  (0x4B)
    uint32_t reserved_76; // offset: 76  (0x4C)
    uint32_t reserved_77; // offset: 77  (0x4D)
    uint32_t reserved_78; // offset: 78  (0x4E)
    uint32_t reserved_79; // offset: 79  (0x4F)
    uint32_t reserved_80; // offset: 80  (0x50)
    uint32_t reserved_81; // offset: 81  (0x51)
    uint32_t reserved_82; // offset: 82  (0x52)
    uint32_t reserved_83; // offset: 83  (0x53)
    uint32_t checksum_lo; // offset: 84  (0x54)
    uint32_t checksum_hi; // offset: 85  (0x55)
    uint32_t cp_mqd_query_time_lo; // offset: 86  (0x56)
    uint32_t cp_mqd_query_time_hi; // offset: 87  (0x57)
    uint32_t reserved_88; // offset: 88  (0x58)
    uint32_t reserved_89; // offset: 89  (0x59)
    uint32_t reserved_90; // offset: 90  (0x5A)
    uint32_t reserved_91; // offset: 91  (0x5B)
    uint32_t cp_mqd_query_wave_count; // offset: 92  (0x5C)
    uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93  (0x5D)
    uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94  (0x5E)
    uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95  (0x5F)
    uint32_t reserved_96; // offset: 96  (0x60)
    uint32_t reserved_97; // offset: 97  (0x61)
    uint32_t reserved_98; // offset: 98  (0x62)
    uint32_t reserved_99