// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 BayLibre, SAS
* Author: Phong LE <ple@baylibre.com>
* Copyright (C) 2018-2019, Artem Mygaiev
* Copyright (C) 2017, Fresco Logic, Incorporated.
*
*/
#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/bitfield.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/of_graph.h>
#include <linux/gpio/consumer.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_edid.h>
#include <drm/drm_modes.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <sound/hdmi-codec.h>
#define IT66121_VENDOR_ID0_REG 0x00
#define IT66121_VENDOR_ID1_REG 0x01
#define IT66121_DEVICE_ID0_REG 0x02
#define IT66121_DEVICE_ID1_REG 0x03
#define IT66121_REVISION_MASK GENMASK(7, 4)
#define IT66121_DEVICE_ID1_MASK GENMASK(3, 0)
#define IT66121_MASTER_SEL_REG 0x10
#define IT66121_MASTER_SEL_HOST BIT(0)
#define IT66121_AFE_DRV_REG 0x61
#define IT66121_AFE_DRV_RST BIT(4)
#define IT66121_AFE_DRV_PWD BIT(5)
#define IT66121_INPUT_MODE_REG 0x70
#define IT66121_INPUT_MODE_RGB (0 << 6)
#define IT66121_INPUT_MODE_YUV422 BIT(6)
#define IT66121_INPUT_MODE_YUV444 (2 << 6)
#define IT66121_INPUT_MODE_CCIR656 BIT(4)
#define IT66121_INPUT_MODE_SYNCEMB BIT(3)
#define IT66121_INPUT_MODE_DDR BIT(2)
#define IT66121_INPUT_CSC_REG 0x72
#define IT66121_INPUT_CSC_ENDITHER BIT(7)
#define IT66121_INPUT_CSC_ENUDFILTER BIT(6)
#define IT66121_INPUT_CSC_DNFREE_GO BIT(5)
#define IT66121_INPUT_CSC_RGB_TO_YUV 0x02
#define IT66121_INPUT_CSC_YUV_TO_RGB 0x03
#define IT66121_INPUT_CSC_NO_CONV 0x00
#define IT66121_AFE_XP_REG 0x62
#define IT66121_AFE_XP_GAINBIT BIT(7)
#define IT66121_AFE_XP_PWDPLL BIT(6)
#define IT66121_AFE_XP_ENI BIT(5)
#define IT66121_AFE_XP_ENO BIT(4)
#define IT66121_AFE_XP_RESETB BIT(3)
#define IT66121_AFE_XP_PWDI BIT(2)
#define IT6610_AFE_XP_BYPASS BIT(0)
#define IT66121_AFE_IP_REG 0x64
#define IT66121_AFE_IP_GAINBIT BIT(7)
#define IT66121_AFE_IP_PWDPLL BIT(6)
#define IT66121_AFE_IP_CKSEL_05 (0 << 4)
#define IT66121_AFE_IP_CKSEL_1 BIT(4)
#define IT66121_AFE_IP_CKSEL_2 (2 << 4)
#define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4)
#define IT66121_AFE_IP_ER0 BIT(3)
#define IT66121_AFE_IP_RESETB BIT(2)
#define IT66121_AFE_IP_ENC BIT(1)
#define IT66121_AFE_IP_EC1 BIT(0)
#define IT
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