path: root/drivers/gpu/drm/bridge/sil-sii8620.h

/*
 * Registers of Silicon Image SiI8620 Mobile HD Transmitter
 *
 * Copyright (C) 2015, Samsung Electronics Co., Ltd.
 * Andrzej Hajda <a.hajda@samsung.com>
 *
 * Based on MHL driver for Android devices.
 * Copyright (C) 2013-2014 Silicon Image, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __SIL_SII8620_H__
#define __SIL_SII8620_H__

/* Vendor ID Low byte, default value: 0x01 */
#define REG_VND_IDL				0x0000

/* Vendor ID High byte, default value: 0x00 */
#define REG_VND_IDH				0x0001

/* Device ID Low byte, default value: 0x60 */
#define REG_DEV_IDL				0x0002

/* Device ID High byte, default value: 0x86 */
#define REG_DEV_IDH				0x0003

/* Device Revision, default value: 0x10 */
#define REG_DEV_REV				0x0004

/* OTP DBYTE510, default value: 0x00 */
#define REG_OTP_DBYTE510			0x0006

/* System Control #1, default value: 0x00 */
#define REG_SYS_CTRL1				0x0008
#define BIT_SYS_CTRL1_OTPVMUTEOVR_SET		BIT(7)
#define BIT_SYS_CTRL1_VSYNCPIN			BIT(6)
#define BIT_SYS_CTRL1_OTPADROPOVR_SET		BIT(5)
#define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD		BIT(4)
#define BIT_SYS_CTRL1_OTP2XVOVR_EN		BIT(3)
#define BIT_SYS_CTRL1_OTP2XAOVR_EN		BIT(2)
#define BIT_SYS_CTRL1_TX_CTRL_HDMI		BIT(1)
#define BIT_SYS_CTRL1_OTPAMUTEOVR_SET		BIT(0)

/* System Control DPD, default value: 0x90 */
#define REG_DPD					0x000b
#define BIT_DPD_PWRON_PLL			BIT(7)
#define BIT_DPD_PDNTX12				BIT(6)
#define BIT_DPD_PDNRX12				BIT(5)
#define BIT_DPD_OSC_EN				BIT(4)
#define BIT_DPD_PWRON_HSIC			BIT(3)
#define BIT_DPD_PDIDCK_N			BIT(2)
#define BIT_DPD_PD_MHL_CLK_N			BIT(1)

/* Dual link Control, default value: 0x00 */
#define REG_DCTL				0x000d
#define BIT_DCTL_TDM_LCLK_PHASE			BIT(7)
#define BIT_DCTL_HSIC_CLK_PHASE			BIT(6)
#define BIT_DCTL_CTS_TCK_PHASE			BIT(5)
#define BIT_DCTL_EXT_DDC_SEL			BIT(4)
#define BIT_DCTL_TRANSCODE			BIT(3)
#define BIT_DCTL_HSIC_RX_STROBE_PHASE		BIT(2)
#define BIT_DCTL_HSIC_TX_BIST_START_SEL		BIT(1)
#define BIT_DCTL_TCLKNX_PHASE			BIT(0)

/* PWD Software Reset, default value: 0x20 */
#define REG_PWD_SRST				0x000e
#define BIT_PWD_SRST_COC_DOC_RST		BIT(7)
#define BIT_PWD_SRST_CBUS_RST_SW		BIT(6)
#define BIT_PWD_SRST_CBUS_RST_SW_EN		BIT(5)
#define BIT_PWD_SRST_MHLFIFO_RST		BIT(4)
#define BIT_PWD_SRST_CBUS_RST			BIT(3)
#define BIT_PWD_SRST_SW_RST_AUTO		BIT(2)
#define BIT_PWD_SRST_HDCP2X_SW_RST		BIT(1)
#define BIT_PWD_SRST_SW_RST			BIT(0)

/* AKSV_1, default value: 0x00 */
#define REG_AKSV_1				0x001d

/* Video H Resolution #1, default value: 0x00 */
#define REG_H_RESL				0x003a

/* Video Mode, default value: 0x00 */
#define REG_VID_MODE				0x004a
#define BIT_VID_MODE_M1080P			BIT(6)

/* Video Input Mode, default value: 0xc0 */
#define REG_VID_OVRRD				0x0051
#define BIT_VID_OVRRD_PP_AUTO_DISABLE		BIT(7)
#define BIT_VID_OVRRD_M1080P_OVRRD		BIT(6)
#define BIT_VID_OVRRD_MINIVSYNC_ON		BIT(5)
#define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK	BIT(4)
#define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN	BIT(3)
#define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD		BIT(2)
#define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD	BIT(0)

/* I2C Address reassignment, default value: 0x00 */
#define REG_PAGE_MHLSPEC_ADDR			0x0057
#define REG_PAGE7_ADDR				0x0058
#define REG_PAGE8_ADDR				0x005c

/* Fast Interrupt Status, default value: 0x00 */
#define REG_FAST_INTR_STAT			0x005f
#define LEN_FAST_INTR_STAT			7
#define BIT_FAST_INTR_STAT_TIMR			8
#define BIT_FAST_INTR_STAT_INT2			9
#define BIT_FAST_INTR_STAT_DDC			10
#define BIT_FAST_INTR_STAT_SCDT			11
#define BIT_FAST_INTR_STAT_INFR			13
#define BIT_FAST_INTR_STAT_EDID			14
#define BIT_FAST_INTR_STAT_HDCP			15
#define BIT_FAST_INTR_STAT_MSC			16
#define BIT_FAST_INTR_STAT_MERR			17
#define BIT_FAST_INTR_STAT_G2WB			18
#define BIT_FAST_INTR_STAT_G2WB_ERR		19
#define BIT_FAST_INTR_STAT_DISC			28
#define BIT_FAST_INTR_STAT_BLOCK		30
#define BIT_FAST_INTR_STAT_LTRN			31
#define BIT_FAST_INTR_STAT_HDCP2		32
#define BIT_FAST_INTR_STAT_TDM			42
#define BIT_FAST_INTR_STAT_COC			51

/* GPIO Control, default value: 0x15 */
#define REG_GPIO_CTRL1				0x006e
#define BIT_CTRL1_GPIO_I_8			BIT(5)
#define BIT_CTRL1_GPIO_OEN_8			BIT(4)
#define BIT_CTRL1_GPIO_I_7			BIT(3)
#define BIT_CTRL1_GPIO_OEN_7			BIT(2)
#define BIT_CTRL1_GPIO_I_6			BIT(1)
#define BIT_CTRL1_GPIO_OEN_6			BIT(0)

/* Interrupt Control, default value: 0x06 */
#define REG_INT_CTRL				0x006f
#define BIT_INT_CTRL_SOFTWARE_WP		BIT(7)
#define BIT_INT_CTRL_INTR_OD			BIT(2)
#define BIT_INT_CTRL_INTR_POLARITY		BIT(1)

/* Interrupt State, default value: 0x00 */
#define REG_INTR_STATE				0x0070
#define BIT_INTR_STATE_INTR_STATE		BIT(0)

/* Interrupt Source #1, default value: 0x00 */
#define REG_INTR1				0x0071

/* Interrupt Source #2, default value: 0x00 */
#define REG_INTR2				0x0072

/* Interrupt Source #3, default value: 0x01 */
#define REG_INTR3				0x0073
#define BIT_DDC_CMD_DONE			BIT(3)

/* Interrupt Source #5, default value: 0x00 */
#define REG_INTR5				0x0074

/* Interrupt #1 Mask, default value: 0x00 */
#define REG_INTR1_MASK				0x0075

/* Interrupt #2 Mask, default value: 0x00 */
#define REG_INTR2_MASK				0x0076

/* Interrupt #3 Mask, default value: 0x00 */
#define REG_INTR3_MASK				0x0077

/* Interrupt #5 Mask, default value: 0x00 */
#define REG_INTR5_MASK				0x0078
#define BIT_INTR_SCDT_CHANGE			BIT(0)

/* Hot Plug Connection Control, default value: 0x45 */
#define REG_HPD_CTRL				0x0079
#define BIT_HPD_CTRL_HPD_DS_SIGNAL		BIT(7)
#define BIT_HPD_CTRL_HPD_OUT_OD_EN		BIT(6)
#define BIT_HPD_CTRL_HPD_HIGH			BIT(5)
#define BIT_HPD_CTRL_HPD_OUT_OVR_EN		BIT(4)
#define BIT_HPD_CTRL_GPIO_I_1			BIT(3)
#define BIT_HPD_CTRL_GPIO_OEN_1			BIT(2)
#define BIT_HPD_CTRL_GPIO_I_0			BIT(1)
#define BIT_HPD_CTRL_GPIO_OEN_0			BIT(0)

/* GPIO Control, default value: 0x55 */
#define REG_GPIO_CTRL				0x007a
#define BIT_CTRL_GPIO_I_5			BIT(7)
#define BIT_CTRL_GPIO_OEN_5			BIT(6)
#define BIT_CTRL_GPIO_I_4			BIT(5)
#define BIT_CTRL_GPIO_OEN_4			BIT(4)
#define BIT_CTRL_GPIO_I_3			BIT(3)
#define BIT_CTRL_GPIO_OEN_3			BIT(2)
#define BIT_CTRL_GPIO_I_2			BIT(1)
#define BIT_CTRL_GPIO_OEN_2			BIT(0)

/* Interrupt Source 7, default value: 0x00 */
#define REG_INTR7				0x007b

/* Interrupt Source 8, default value: 0x00 */
#define REG_INTR8				0x007c

/* Interrupt #7 Mask, default value: 0x00 */
#define REG_INTR7_MASK				0x007d

/* Interrupt #8 Mask, default value: 0x00 */
#define REG_INTR8_MASK				0x007e
#define BIT_CEA_NEW_VSI				BIT(2)
#define BIT_CEA_NEW_AVI				BIT(1)

/* IEEE, default value: 0x10 */
#define REG_TMDS_CCTRL				0x0080
#define BIT_TMDS_CCTRL_TMDS_OE			BIT(4)

/* TMDS Control #4, default value: 0x02 */
#define REG_TMDS_CTRL4				0x0085
#define BIT_TMDS_CTRL4_SCDT_CKDT_SEL		BIT(1)
#define BIT_TMDS_CTRL4_TX_EN_BY_SCDT		BIT(0)

/* BIST CNTL, default value: 0x00 */
#define REG_BIST_CTRL				0x00bb
#define BIT_RXBIST_VGB_EN			BIT(7)
#define BIT_TXBIST_VGB_EN			BIT(6)
#define BIT_BIST_START_SEL			BIT(5)
#define BIT_BIST_START_BIT			BIT(4)
#define BIT_BIST_ALWAYS_ON			BIT(3)
#define BIT_BIST_TRANS				BIT(2)
#define BIT_BIST_R