// SPDX-License-Identifier: MIT
/*
* Copyright © 2008-2021 Intel Corporation
*/
#include "gen2_engine_cs.h"
#include "gen6_engine_cs.h"
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_gt.h"
#include "intel_reset.h"
#include "intel_ring.h"
#include "shmem_utils.h"
/* Rough estimate of the typical request size, performing a flush,
* set-context and then emitting the batch.
*/
#define LEGACY_REQUEST_SIZE 200
static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
{
/*
* Keep the render interrupt unmasked as this papers over
* lost interrupts following a reset.
*/
if (engine->class == RENDER_CLASS) {
if (INTEL_GEN(engine->i915) >= 6)
mask &= ~BIT(0);
else
mask &= ~I915_USER_INTERRUPT;
}
intel_engine_set_hwsp_writemask(engine, mask);
}
static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
{
u32 addr;
addr = lower_32_bits(phys);
if (INTEL_GEN(engine->i915) >= 4)
addr |= (phys >> 28) & 0xf0;
intel_uncore_write(engine->uncore, HWS_PGA, addr);
}
static struct page *status_page(struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
return sg_page(obj->mm.pages->sgl);
}
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
{
set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
set_hwstam(engine, ~0u);
}
static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
{
i915_reg_t hwsp;
/*
* The ring status page addresses are no longer next to the rest of
* the ring registers as of gen7.
*/
if (IS_GEN(engine->i915, 7)) {
switch (engine->id) {
/*
* No more rings exist on Gen7. Default case is only to shut up
* gcc switch check warning.
*/
default:
GEM_BUG_ON(engine->id);
fallthrough;
case RCS0:
hwsp = RENDER_HWS_PGA_GEN7;
break;
case BCS0:
hwsp = BLT_HWS_PGA_GEN7;
break;
case VCS0:
hwsp = BSD_HWS_PGA_GEN7;
break;
case VECS0:
hwsp = VEBOX_HWS_PGA_GEN7;
break;
}
} else if (IS_GEN(engine->i915, 6)) {
hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
hwsp = RING_HWS_PGA(engine->mmio_base);
}
intel_uncore_write_fw(engine->uncore, hwsp, offset);
intel_uncore_posting_read_fw(engine->uncore, hwsp);
}
static 