// SPDX-License-Identifier: MIT
/*
* Copyright © 2021-2022 Intel Corporation
*/
#include <linux/types.h>
#include <drm/drm_print.h>
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc.h"
#include "guc_capture_fwif.h"
#include "intel_guc_capture.h"
#include "intel_guc_fwif.h"
#include "intel_guc_print.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
#include "i915_reg.h"
/*
* Define all device tables of GuC error capture register lists
* NOTE: For engine-registers, GuC only needs the register offsets
* from the engine-mmio-base
*/
#define COMMON_BASE_GLOBAL \
{ FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
#define COMMON_GEN8BASE_GLOBAL \
{ ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
{ DONE_REG, 0, 0, "DONE_REG" }, \
{ HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
#define GEN8_GLOBAL \
{ GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
{ GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
#define COMMON_GEN12BASE_GLOBAL \
{ GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
{ GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
{ GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG" }, \
{ GEN12_GAM_DONE, 0, 0, "GAM_DONE" }, \
{ GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG" }
#define COMMON_BASE_ENGINE_INSTANCE \
{ RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \
{ RING_ESR(0), 0, 0, "ESR" }, \
{ RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW" }, \
{ RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW" }, \
{ RING_IPEIR(0), 0, 0, "IPEIR" }, \
{ RING_IPEHR(0), 0, 0, "IPEHR" }, \
{ RING_INSTPS(0), 0, 0, "INSTPS" }, \
{ RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32" }, \
{ RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32" }, \
{ RING_BBSTATE(0), 0, 0, "BB_STATE" }, \
{ CCID(0), 0, 0, "CCID" }, \
{ RING_ACTHD(0), 0, 0, "ACTHD_LDW" }, \
{ RING_ACTHD_UDW(0
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