path: root/drivers/gpu/drm/i915/intel_gvt_mmio_table.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020 Intel Corporation
 */

#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_color_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
#include "display/intel_dpio_phy.h"
#include "display/intel_fdi_regs.h"
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#include "gvt/reg.h"

#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
#include "intel_gvt.h"
#include "intel_mchbar_regs.h"

#define MMIO_F(reg, s) do { \
	int ret; \
	ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \
	if (ret) \
		return ret; \
} while (0)

#define MMIO_D(reg) MMIO_F(reg, 4)

#define MMIO_RING_F(prefix, s) do { \
	MMIO_F(prefix(RENDER_RING_BASE), s); \
	MMIO_F(prefix(BLT_RING_BASE), s); \
	MMIO_F(prefix(GEN6_BSD_RING_BASE), s); \
	MMIO_F(prefix(VEBOX_RING_BASE), s); \
	if (HAS_ENGINE(to_gt(iter->i915), VCS1)) \
		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s); \
} while (0)

#define MMIO_RING_D(prefix) \
	MMIO_RING_F(prefix, 4)

static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
{
	struct drm_i915_private *dev_priv = iter->i915;

	MMIO_RING_D(RING_IMR);
	MMIO_D(SDEIMR);
	MMIO_D(SDEIER);
	MMIO_D(SDEIIR);
	MMIO_D(SDEISR);
	MMIO_RING_D(RING_HWSTAM);
	MMIO_D(BSD_HWS_PGA_GEN7);
	MMIO_D(BLT_HWS_PGA_GEN7);
	MMIO_D(VEBOX_HWS_PGA_GEN7);

#define RING_REG(base) _MMIO((base) + 0x28)
	MMIO_RING_D(RING_REG);
#undef RING_REG

#define RING_REG(base) _MMIO((base) + 0x134)
	MMIO_RING_D(RING_REG);
#undef RING_REG

#define RING_REG(base) _MMIO((base) + 0x6c)
	MMIO_RING_D(RING_REG);
#undef RING_REG
	MMIO_D(_MMIO(0x2148));
	MMIO_D(CCID(RENDER_RING_BASE));
	MMIO_D(_MMIO(0x12198));
	MMIO_D(GEN7_CXT_SIZE);
	MMIO_RING_D(RING_TAIL);
	MMIO_RING_D(RING_HEAD);
	MMIO_RING_D(RING_CTL);
	MMIO_RING_D(RING_ACTHD);
	MMIO_RING_D(RING_START);

	/* RING MODE */
#define RING_REG(base) _MMIO((base) + 0x29c)
	MMIO_RING_D(RING_REG);
#undef RING_REG

	MMIO_RING_D(RING_MI_MODE);
	MMIO_RING_D(RING_INSTPM);
	MMIO_RING_D(RING_TIMESTAMP);
	MMIO_RING_D(RING_TIMESTAMP_UDW);
	MMIO_D(GEN7_GT_MODE);
	MMIO_D(CACHE_MODE_0_GEN7);
	MMIO_D(CACHE_MODE_1);
	MMIO_D(CACHE_MODE_0);
	MMIO_D(_MMIO(0x2124));
	MMIO_D(_MMIO(0x20dc));
	MMIO_D(_3D_CHICKEN3);
	MMIO_D(_MMIO(0x2088));
	MMIO_D(FF_SLICE_CS_CHICKEN2);
	MMIO_D(_MMIO(0x2470));
	MMIO_D(GAM_ECOCHK);
	MMIO_D(GEN7_COMMON_SLICE_CHICKEN1);
	MMIO_D(COMMON_SLICE_CHICKEN2);
	MMIO_D(_MMIO(0x9030));
	MMIO_D(_MMIO(0x20a0));
	MMIO_D(_MMIO(0x2420));
	MMIO_D(_MMIO(0x2430));
	MMIO_D(_MMIO(0x2434));
	MMIO_D(_MMIO(0x2438));
	MMIO_D(_MMIO(0x243c));
	MMIO_D(_MMIO(0x7018));
	MMIO_D(HSW_HALF_SLICE_CHICKEN3);
	MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
	/* display */
	MMIO_F(_MMIO(0x60220), 0x20</