path: root/drivers/gpu/drm/kmb/kmb_drv.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright © 2018-2020 Intel Corporation
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_graph.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_fbdev_dma.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_module.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>

#include "kmb_drv.h"
#include "kmb_dsi.h"
#include "kmb_regs.h"

static int kmb_display_clk_enable(struct kmb_drm_private *kmb)
{
	int ret = 0;

	ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd);
	if (ret) {
		drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret);
		return ret;
	}
	DRM_INFO("SUCCESS : enabled LCD clocks\n");
	return 0;
}

static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev)
{
	int ret = 0;
	struct regmap *msscam;

	kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd");
	if (IS_ERR(kmb->kmb_clk.clk_lcd)) {
		drm_err(&kmb->drm, "clk_get() failed clk_lcd\n");
		return PTR_ERR(kmb->kmb_clk.clk_lcd);
	}

	kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0");
	if (IS_ERR(kmb->kmb_clk.clk_pll0)) {
		drm_err(&kmb->drm, "clk_get() failed clk_pll0 ");
		return PTR_ERR(kmb->kmb_clk.clk_pll0);
	}
	kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000;
	drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz);

	ret =  kmb_dsi_clk_init(kmb->kmb_dsi);

	/* Set LCD clock to 200 Mhz */
	clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK);
	if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) {
		drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n",
			KMB_LCD_DEFAULT_CLK);
		return -1;
	}
	drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd));

	ret = kmb_display_clk_enable(kmb);
	if (ret)
		return ret;

	msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
	if (IS_ERR(msscam)) {
		drm_err(&kmb->drm, "failed to get msscam syscon");
		return -1;
	}

	/* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
	regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff);
	regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff);
	return 0;
}

static void kmb_display_clk_disable(struct kmb_drm_private *kmb)
{
	clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
}

static void __iomem *kmb_map_mmio(struct drm_device *drm,
				  struct platform_device *pdev,
				  char *name)
{
	struct resource *res;
	void __iomem *mem;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	if (!res) {
		drm_err(drm, "failed to get resource for %s", name);
		return ERR_PTR(-ENOMEM);
	}
	mem = devm_ioremap_resource(drm->dev, res);
	if (IS_ERR(mem))
		drm_err(drm, "failed to ioremap %s registers", name);
	return mem;
}

static int kmb_hw_init(struct drm_device *drm, unsigned long flags)
{
	struct kmb_drm_private *kmb = to_kmb(drm);
	struct platform_device *pdev = to_platform_device(drm->dev);
	int irq_lcd;
	int ret = 0;

	/* Map LCD MMIO registers */
	kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd");
	if (IS_ERR(kmb->lcd_mmio)) {
		drm_err(&kmb->drm, "failed to map LCD registers\n");
		return -ENOMEM;
	}

	/* Map MIPI MMIO registers */
	ret = kmb_dsi_map_mmio(kmb->kmb_dsi);
	if (ret)
		return ret;

	/* Enable display clocks */
	kmb_initialize_clocks(kmb, &pdev->dev);

	/* Register irqs here - section 17.3 in databook
	 * lists LCD at 79 and 82 for MIPI under MSS CPU -
	 * firmware has redirected 79 to A53 IRQ 33
	 */

	/* Allocate LCD interrupt resources */
	irq_lcd = platform_get_irq(pdev, 0);
	if (irq_lcd < 0) {
		ret = irq_lcd;
		drm_err(&kmb->drm, "irq_lcd not found");
		goto setup_fail;
	}

	/* Get the optional framebuffer memory resource */
	ret = of_reserved_mem_device_init(drm->dev);
	if (ret && ret != -ENODEV)
		return ret;

	spin_lock_init(&kmb->irq_lock);

	kmb->irq_lcd = irq_lcd;

	return 0;

 setup_fail:
	of_reserved_mem_device_release(drm->dev);

	return ret;
}

static const struct drm_mode_config_funcs kmb_mode_config_funcs = {
	.fb_create = drm_gem_fb_create,
	.atomic_check = drm_atomic_helper_check,
	.atomic_commit = drm_atomic_helper_commit,
};

static int kmb_setup_mode_config(struct drm_device *drm)
{
	int ret;
	struct kmb_drm_private *kmb = to_kmb(drm);

	ret = drmm_mode_config_init(drm);
	if (ret)
		return ret;
	drm->mode_config.min_width = KMB_FB_MIN_WIDTH;
	drm->mode_config.min_height = KMB_FB_MIN_HEIGHT;
	drm->mode_config.max_width = KMB_FB_MAX_WIDTH;
	drm->mode_config.max_height = KMB_FB_MAX_HEIGHT;
	drm->mode_config.preferred_depth = 24;
	drm->mode_config.funcs = &kmb_mode_config_funcs;

	ret = kmb_setup_crtc(drm);
	if (ret < 0) {
		drm_err(drm, "failed to create crtc\n");
		return ret;
	}
	ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi);
	/* Set the CRTC's port so that the encoder component can find it */
	kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0);
	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
	if (ret < 0) {
		drm_err(drm, "failed to initialize vblank\n");
		pm_runtime_disable(drm->dev);
		return ret;
	}

	drm_mode_config_reset(drm);
	return 0;
}

static irqreturn_t handle_lcd_irq(struct drm_device *dev)
{
	unsigned long status, val, val1;
	int plane_id, dma0_state, dma1_state;
	struct kmb_drm_private *kmb = to_kmb(dev);
	u32 ctrl = 0;

	status = kmb_read_lcd(kmb, LCD_INT_STATUS);

	spin_lock(&kmb->irq_lock);
	if (status & LCD_INT_EOF) {
		kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF);

		/* When disabling/enabling LCD layers, the change takes effect
		 * immediately and does not wait for EOF (end of frame).
		 * When kmb_plane_atomic_disable is called, mark the plane as
		 * disabled but actually disable the plane when EOF irq is
		 * being handled.
		 */
		for (plane_id = LAYER_0;
				plane_id < KMB_MAX_PLANES; plane_id++) {
			if (kmb->plane_status[plane_id].disable) {
				kmb_clr_bitmask_lcd(kmb,
						    LCD_LAYERn_DMA_CFG
						    (plane_id),
						    LCD_DMA_LAYER_ENABLE);

				kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
						    kmb->plane_status[plane_id].ctrl);

				ctrl = kmb_read_lcd(kmb, LCD_CONTROL);
				if (!(ctrl & (LCD_CTRL_VL1_ENABLE |
				    LCD_CTRL_VL2_ENABLE |
				    LCD_CTRL_GL1_ENABLE |
				    LCD_CTRL_GL2_ENABLE))) {
					/* If no LCD layers are using DMA,
					 * then disable DMA pipelined AXI read
					 * transactions.
					 */
					kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
							    LCD_CTRL_PIPELINE_DMA);
				}

				kmb->plane_status[plane_id].disable = false;
			}
		}
		if (kmb->kmb_under_flow) {
			/* DMA Recovery after underflow */
			dma0_state = (kmb->layer_no == 0) ?
			    LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE;
			dma1_state = (kmb->layer_no == 0) ?
			    LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE;

			do {
				kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
				val = kmb_read_lcd(kmb, dma0_state)
				    & LCD_DMA_STATE_ACTIVE;
				val1 = kmb_read_lcd(kmb, dma1_state)
				    & LCD_DMA_STATE_ACTIVE;
			} while ((val || val1));
			/* disable dma */
			kmb_clr_bitmask_lcd(kmb,
					    LCD_LAYERn_DMA_CFG(kmb->layer_no),
					    LCD_DMA_LAYER_ENABLE);
			kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);</