// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
#include <linux/ascii85.h>
#include "msm_gem.h"
#include "a6xx_gpu.h"
#include "a6xx_gmu.h"
#include "a6xx_gpu_state.h"
#include "a6xx_gmu.xml.h"
struct a6xx_gpu_state_obj {
const void *handle;
u32 *data;
};
struct a6xx_gpu_state {
struct msm_gpu_state base;
struct a6xx_gpu_state_obj *gmu_registers;
int nr_gmu_registers;
struct a6xx_gpu_state_obj *registers;
int nr_registers;
struct a6xx_gpu_state_obj *shaders;
int nr_shaders;
struct a6xx_gpu_state_obj *clusters;
int nr_clusters;
struct a6xx_gpu_state_obj *dbgahb_clusters;
int nr_dbgahb_clusters;
struct a6xx_gpu_state_obj *indexed_regs;
int nr_indexed_regs;
struct a6xx_gpu_state_obj *debugbus;
int nr_debugbus;
struct a6xx_gpu_state_obj *vbif_debugbus;
struct a6xx_gpu_state_obj *cx_debugbus;
int nr_cx_debugbus;
struct msm_gpu_state_bo *gmu_log;
struct msm_gpu_state_bo *gmu_hfi;
struct msm_gpu_state_bo *gmu_debug;
s32 hfi_queue_history[2][HFI_HISTORY_SZ];
struct list_head objs;
bool gpu_initialized;
};
static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val)
{
in[0] = val;
in[1] = (((u64) reg) << 44 | 