path: root/drivers/gpu/drm/nouveau/dispnv50/crc.c

// SPDX-License-Identifier: MIT
#include <linux/string.h>
#include <drm/drm_crtc.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_vblank.h>
#include <drm/drm_vblank_work.h>

#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/timer.h>

#include <nvhw/class/cl907d.h>

#include "nouveau_drv.h"
#include "core.h"
#include "head.h"
#include "wndw.h"
#include "handles.h"
#include "crc.h"

static const char * const nv50_crc_sources[] = {
	[NV50_CRC_SOURCE_NONE] = "none",
	[NV50_CRC_SOURCE_AUTO] = "auto",
	[NV50_CRC_SOURCE_RG] = "rg",
	[NV50_CRC_SOURCE_OUTP_ACTIVE] = "outp-active",
	[NV50_CRC_SOURCE_OUTP_COMPLETE] = "outp-complete",
	[NV50_CRC_SOURCE_OUTP_INACTIVE] = "outp-inactive",
};

static int nv50_crc_parse_source(const char *buf, enum nv50_crc_source *s)
{
	int i;

	if (!buf) {
		*s = NV50_CRC_SOURCE_NONE;
		return 0;
	}

	i = match_string(nv50_crc_sources, ARRAY_SIZE(nv50_crc_sources), buf);
	if (i < 0)
		return i;

	*s = i;
	return 0;
}

int
nv50_crc_verify_source(struct drm_crtc *crtc, const char *source_name,
		       size_t *values_cnt)
{
	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
	enum nv50_crc_source source;

	if (nv50_crc_parse_source(source_name, &source) < 0) {
		NV_DEBUG(drm, "unknown source %s\n", source_name);
		return -EINVAL;
	}

	*values_cnt = 1;
	return 0;
}

const char *const *nv50_crc_get_sources(struct drm_crtc *crtc, size_t *count)
{
	*count = ARRAY_SIZE(nv50_crc_sources);
	return nv50_crc_sources;
}

static void
nv50_crc_program_ctx(struct nv50_head *head,
		     struct nv50_crc_notifier_ctx *ctx)
{
	struct nv50_disp *disp = nv50_disp(head->base.base.dev);
	struct nv50_core *core = disp->core;
	u32 interlock[NV50_DISP_INTERLOCK__SIZE] = { 0 };

	core->func->crc->set_ctx(head, ctx);
	core->func->update(core, interlock, false);
}

static void nv50_crc_ctx_flip_work(struct kthread_work *base)
{
	struct drm_vblank_work *work = to_drm_vblank_work(base);
	struct nv50_crc *crc = container_of(work, struct nv50_crc, flip_work);
	struct nv50_head *head = container_of(crc, struct nv50_head, crc);
	struct drm_crtc *crtc = &head->base.base;
	struct nv50_disp *disp = nv50_disp(crtc->dev);
	u8 new_idx = crc->ctx_idx ^ 1;

	/*
	 * We don't want to accidentally wait for longer then the vblank, so
	 * try again for the next vblank if we don't grab the lock
	 */
	if (!mutex_trylock(&disp->mutex)) {
		DRM_DEV_DEBUG_KMS(crtc->dev->dev,
				  "Lock contended, delaying CRC ctx flip for head-%d\n",
				  head->base.index);
		drm_vblank_work_schedule(work,
					 drm_crtc_vblank_count(crtc) + 1,
					 true);
		return;
	}

	DRM_DEV_DEBUG_KMS(crtc->dev->dev,
			  "Flipping notifier ctx for head %d (%d -> %d)\n",
			  drm_crtc_index(crtc), crc->ctx_idx, new_idx);

	nv50_crc_program_ctx(head, NULL);
	nv50_crc_program_ctx(head, &crc->ctx[new_idx]);
	mutex_unlock(&disp->mutex);

	spin_lock_irq(&crc->lock);
	crc->ctx_changed = true;
	spin_unlock_irq(&crc->lock);
}

static inline void nv50_crc_reset_ctx(struct nv50_crc_notifier_ctx *ctx)
{
	memset_io(ctx->mem.object.map.ptr, 0, ctx->mem.object.map.size);
}

static void
nv50_crc_get_entries(struct nv50_head *head,
		     const struct nv50_crc_func *func,
		     enum nv50_crc_source source)
{
	struct drm_crtc *crtc = &head->base.base;
	struct nv50_crc *crc = &head->crc;
	u32 output_crc;

	while (crc->entry_idx < func->num_entries) {
		/*
		 * While Nvidia's documentation says CRCs are written on each
		 * subsequent vblank after being enabled, in practice they
		 * aren't written immediately.
		 */
		output_crc = func->get_entry(head, &crc->ctx[crc->ctx_idx],
					     source, crc->entry_idx);
		if (!output_crc)
			return;

		drm_crtc_add_crc_entry(crtc, true, crc->frame, &output_crc);
		crc->frame++;
		crc->entry_idx++;
	}
}

void nv50_crc_handle_vblank(struct nv50_head *head)
{
	struct drm_crtc *crtc = &head->base.base;
	struct nv50_crc *crc = &head->crc;
	const struct nv50_crc_func *func =
		nv50_disp(head->base.base.dev)->core->func->crc;
	struct nv50_crc_notifier_ctx *ctx;
	bool need_reschedule = false;

	if (!func)
		return;

	/*
	 * We don't lose events if we aren't able to report CRCs until the
	 * next vblank, so only report CRCs if the locks we need aren't
	 * contended to prevent missing an actual vblank event
	 */
	if (!spin_trylock(&crc->lock))
		return;

	if (!crc->src)
		goto out;

	ctx = &crc->ctx[crc->ctx_idx];
	if (crc->ctx_changed && func->ctx_finished(head, ctx)) {
		nv50_crc_get_entries(head, func, crc->src);

		crc->ctx_idx ^= 1;
		crc->entry_idx = 0;
		crc->ctx_changed = false;

		/*
		 * Unfortunately when notifier contexts are changed during CRC
		 * capture, we will inevitably lose the CRC entry for the
		 * frame where the hardware actually latched onto the first
		 * UPDATE. According to Nvidia's hardware engineers, there's
		 * no workaround for this.
		 *
		 * Now, we could try to be smart here and calculate the number
		 * of missed CRCs based on audit timestamps, but those were
		 * removed starting with volta. Since we always flush our
		 * updates back-to-back without waiting, we'll just be
		 * optimistic and assume we always miss exactly one frame.
		 */
		DRM_DEV_DEBUG_KMS(head->base.base.dev->dev,
				  "Notifier ctx flip for head-%d finished, lost CRC for frame %llu\n",
				  head->base.index, crc->frame);
		crc->frame++;

		nv50_crc_reset_ctx(ctx);
		need_reschedule = true;
	}

	nv50_crc_get_entries(head, func, crc->src);

	if (need_reschedule)
		drm_vblank_work_schedule(&crc->flip_work,
					 drm_crtc_vblank_count(crtc)
					 + crc->flip_threshold
					 - crc->entry_idx,
					 true);

out:
	spin_unlock(&crc->lock);
}

static void nv50_crc_wait_ctx_finished(struct nv50_head *head,
				       const struct nv50_crc_func *func,
				       struct nv50_crc_notifier_ctx *ctx)
{
	struct drm_device *dev = head->base.base.dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	s64 ret;

	ret = nvif_msec(&drm->client.device, 50,
			if (func->ctx_finished(head, ctx)) break;);
	if (ret == -ETIMEDOUT)
		NV_ERROR(drm,
			 "CRC notifier ctx for head %d not finished after 50ms\n",
			 head->base.index);
	else if (ret)
		NV_ATOMIC(drm,
			  "CRC notifier ctx for head-%d finished after %lldns\n",
			  head->base.index, ret);
}

void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state)
{
	struct drm_crtc_state *crtc_state