path: root/drivers/gpu/drm/panel/panel-himax-hx83102.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for panels based on Himax HX83102 controller, such as:
 *
 * - Starry 10.51" WUXGA MIPI-DSI panel
 *
 * Based on drivers/gpu/drm/panel/panel-himax-hx8394.c
 */

#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>

#include <drm/drm_connector.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>

#include <video/mipi_display.h>

/* Manufacturer specific DSI commands */
#define HX83102_SETPOWER	0xb1
#define HX83102_SETDISP		0xb2
#define HX83102_SETCYC		0xb4
#define HX83102_UNKNOWN_B6	0xb6
#define HX83102_UNKNOWN_B8	0xb8
#define HX83102_SETEXTC		0xb9
#define HX83102_SETMIPI		0xba
#define HX83102_SETVDC		0xbc
#define HX83102_SETBANK		0xbd
#define HX83102_UNKNOWN_BE	0xbe
#define HX83102_SETPTBA		0xbf
#define HX83102_SETSTBA		0xc0
#define HX83102_SETTCON		0xc7
#define HX83102_SETRAMDMY	0xc8
#define HX83102_SETPWM		0xc9
#define HX83102_SETCLOCK	0xcb
#define HX83102_SETPANEL	0xcc
#define HX83102_SETCASCADE	0xd0
#define HX83102_SETPCTRL	0xd1
#define HX83102_UNKNOWN_D2	0xd2
#define HX83102_SETGIP0		0xd3
#define HX83102_SETGIP1		0xd5
#define HX83102_SETGIP2		0xd6
#define HX83102_SETGIP3		0xd8
#define HX83102_UNKNOWN_D9	0xd9
#define HX83102_SETGMA		0xe0
#define HX83102_UNKNOWN_E1	0xe1
#define HX83102_SETTP1		0xe7
#define HX83102_SETSPCCMD	0xe9

struct hx83102 {
	struct drm_panel base;
	struct mipi_dsi_device *dsi;

	const struct hx83102_panel_desc *desc;

	enum drm_panel_orientation orientation;
	struct regulator *pp1800;
	struct regulator *avee;
	struct regulator *avdd;
	struct gpio_desc *enable_gpio;
};

struct hx83102_panel_desc {
	const struct drm_display_mode *modes;

	/**
	 * @width_mm: width of the panel's active display area
	 * @height_mm: height of the panel's active display area
	 */
	struct {
		unsigned int width_mm;
		unsigned int height_mm;
	} size;

	int (*init)(struct hx83102 *ctx);
};

static inline struct hx83102 *panel_to_hx83102(struct drm_panel *panel)
{
	return container_of(panel, struct hx83102, base);
}

static void hx83102_enable_extended_cmds(struct mipi_dsi_multi_context *dsi_ctx, bool enable)
{
	if (enable)
		mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00);
	else
		mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x00, 0x00, 0x00);
}

static int starry_himax83102_j02_init(struct hx83102 *ctx)
{
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };

	hx83102_enable_extended_cmds(&dsi_ctx, true);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1,
				     0x31, 0xd7, 0x2f, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11,
				     0x65, 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x74,
				     0x33);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00,
				     0x12, 0x72, 0x3c, 0xa3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xf5);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x76, 0x76, 0x76, 0x76, 0x76,
				     0x76, 0x63, 0x5c, 0x63, 0x5c, 0x01, 0x9e);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0x36, 0x22, 0x11, 0x22,
				     0xa0, 0x61, 0x08, 0xf5, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x33);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c,
				     0xff);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f, 0x11, 0x1f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx<