path: root/drivers/gpu/drm/rockchip/rockchip_vop_reg.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <mark.yao@rock-chips.com>
 */

#ifndef _ROCKCHIP_VOP_REG_H
#define _ROCKCHIP_VOP_REG_H

/* rk3288 register definition */
#define RK3288_REG_CFG_DONE			0x0000
#define RK3288_VERSION_INFO			0x0004
#define RK3288_SYS_CTRL				0x0008
#define RK3288_SYS_CTRL1			0x000c
#define RK3288_DSP_CTRL0			0x0010
#define RK3288_DSP_CTRL1			0x0014
#define RK3288_DSP_BG				0x0018
#define RK3288_MCU_CTRL				0x001c
#define RK3288_INTR_CTRL0			0x0020
#define RK3288_INTR_CTRL1			0x0024
#define RK3288_WIN0_CTRL0			0x0030
#define RK3288_WIN0_CTRL1			0x0034
#define RK3288_WIN0_COLOR_KEY			0x0038
#define RK3288_WIN0_VIR				0x003c
#define RK3288_WIN0_YRGB_MST			0x0040
#define RK3288_WIN0_CBR_MST			0x0044
#define RK3288_WIN0_ACT_INFO			0x0048
#define RK3288_WIN0_DSP_INFO			0x004c
#define RK3288_WIN0_DSP_ST			0x0050
#define RK3288_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3288_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3288_WIN0_SCL_OFFSET			0x005c
#define RK3288_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3288_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3288_WIN0_FADING_CTRL			0x0068
#define RK3288_WIN0_CTRL2			0x006c

/* win1 register */
#define RK3288_WIN1_CTRL0			0x0070
#define RK3288_WIN1_CTRL1			0x0074
#define RK3288_WIN1_COLOR_KEY			0x0078
#define RK3288_WIN1_VIR				0x007c
#define RK3288_WIN1_YRGB_MST			0x0080
#define RK3288_WIN1_CBR_MST			0x0084
#define RK3288_WIN1_ACT_INFO			0x0088
#define RK3288_WIN1_DSP_INFO			0x008c
#define RK3288_WIN1_DSP_ST			0x0090
#define RK3288_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3288_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3288_WIN1_SCL_OFFSET			0x009c
#define RK3288_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3288_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3288_WIN1_FADING_CTRL			0x00a8
/* win2 register */
#define RK3288_WIN2_CTRL0			0x00b0
#define RK3288_WIN2_CTRL1			0x00b4
#define RK3288_WIN2_VIR0_1			0x00b8
#define RK3288_WIN2_VIR2_3			0x00bc
#define RK3288_WIN2_MST0			0x00c0
#define RK3288_WIN2_DSP_INFO0			0x00c4
#define RK3288_WIN2_DSP_ST0			0x00c8
#define RK3288_WIN2_COLOR_KEY			0x00cc
#define RK3288_WIN2_MST1			0x00d0
#define RK3288_WIN2_DSP_INFO1			0x00d4
#define RK3288_WIN2_DSP_ST1			0x00d8
#define RK3288_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3288_WIN2_MST2			0x00e0
#define RK3288_WIN2_DSP_INFO2			0x00e4
#define RK3288_WIN2_DSP_ST2			0x00e8
#define RK3288_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3288_WIN2_MST3			0x00f0
#define RK3288_WIN2_DSP_INFO3			0x00f4
#define RK3288_WIN2_DSP_ST3			0x00f8
#define RK3288_WIN2_FADING_CTRL			0x00fc
/* win3 register */
#define RK3288_WIN3_CTRL0			0x0100
#define RK3288_WIN3_CTRL1			0x0104
#define RK3288_WIN3_VIR0_1			0x0108
#define RK3288_WIN3_VIR2_3			0x010c
#define RK3288_WIN3_MST0			0x0110
#define RK3288_WIN3_DSP_INFO0			0x0114
#define RK3288_WIN3_DSP_ST0			0x0118
#define RK3288_WIN3_COLOR_KEY			0x011c
#define RK3288_WIN3_MST1			0x0120
#define RK3288_WIN3_DSP_INFO1			0x0124
#define RK3288_WIN3_DSP_ST1			0x0128
#define RK3288_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3288_WIN3_MST2			0x0130
#define RK3288_WIN3_DSP_INFO2			0x0134
#define RK3288_WIN3_DSP_ST2			0x0138
#define RK3288_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3288_WIN3_MST3			0x0140
#define RK3288_WIN3_DSP_INFO3			0x0144
#define RK3288_WIN3_DSP_ST3			0x0148
#define RK3288_WIN3_FADING_CTRL			0x014c
/* hwc register */
#define RK3288_HWC_CTRL0			0x0150
#define RK3288_HWC_CTRL1			0x0154
#define RK3288_HWC_MST				0x0158
#define RK3288_HWC_DSP_ST			0x015c
#define RK3288_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3288_HWC_DST_ALPHA_CTRL		0x0164
#define RK3288_HWC_FADING_CTRL			0x0168
/* post process register */
#define RK3288_POST_DSP_HACT_INFO		0x0170
#define RK3288_POST_DSP_VACT_INFO		0x0174
#define RK3288_POST_SCL_FACTOR_YRGB		0x0178
#define RK3288_POST_SCL_CTRL			0x0180
#define RK3288_POST_DSP_VACT_INFO_F1		0x0184
#define RK3288_DSP_HTOTAL_HS_END		0x0188
#define RK3288_DSP_HACT_ST_END			0x018c
#define RK3288_DSP_VTOTAL_VS_END		0x0190
#define RK3288_DSP_VACT_ST_END			0x0194
#define RK3288_DSP_VS_ST_END_F1			0x0198
#define RK3288_DSP_VACT_ST_END_F1		0x019c
/* register definition end */

/* rk3368 register definition */
#define RK3368_REG_CFG_DONE			0x0000
#define RK3368_VERSION_INFO			0x0004
#define RK3368_SYS_CTRL				0x0008
#define RK3368_SYS_CTRL1			0x000c
#define RK3368_DSP_CTRL0			0x0010
#define RK3368_DSP_CTRL1			0x0014
#define RK3368_DSP_BG				0x0018
#define RK3368_MCU_CTRL				0x001c
#define RK3368_LINE_FLAG			0x0020
#define RK3368_INTR_EN				0x0024
#define RK3368_INTR_CLEAR			0x0028
#define RK3368_INTR_STATUS			0x002c
#define RK3368_WIN0_CTRL0			0x0030
#define RK3368_WIN0_CTRL1			0x0034
#define RK3368_WIN0_COLOR_KEY			0x0038
#define RK3368_WIN0_VIR				0x003c
#define RK3368_WIN0_YRGB_MST			0x0040
#define RK3368_WIN0_CBR_MST			0x0044
#define RK3368_WIN0_ACT_INFO			0x0048
#define RK3368_WIN0_DSP_INFO			0x004c
#define RK3368_WIN0_DSP_ST			0x0050
#define RK3368_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3368_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3368_WIN0_SCL_OFFSET			0x005c
#define RK3368_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3368_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3368_WIN0_FADING_CTRL			0x0068
#define RK3368_WIN0_CTRL2			0x006c
#define RK3368_WIN1_CTRL0			0x0070
#define RK3368_WIN1_CTRL1			0x0074
#define RK3368_WIN1_COLOR_KEY			0x0078
#define RK3368_WIN1_VIR				0x007c
#define RK3368_WIN1_YRGB_MST			0x0080
#define RK3368_WIN1_CBR_MST			0x0084
#define RK3368_WIN1_ACT_INFO			0x0088
#define RK3368_WIN1_DSP_INFO			0x008c
#define RK3368_WIN1_DSP_ST			0x0090
#define RK3368_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3368_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3368_WIN1_SCL_OFFSET			0x009c
#define RK3368_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3368_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3368_WIN1_FADING_CTRL			0x00a8
#define RK3368_WIN1_CTRL2			0x00ac
#define RK3368_WIN2_CTRL0			0x00b0
#define RK3368_WIN2_CTRL1			0x00b4
#define RK3368_WIN2_VIR0_1			0x00b8
#define RK3368_WIN2_VIR2_3			0x00bc
#define RK3368_WIN2_MST0			0x00c0
#define RK3368_WIN2_DSP_INFO0			0x00c4
#define RK3368_WIN2_DSP_ST0			0x00c8
#define RK3368_WIN2_COLOR_KEY			0x00cc
#define RK3368_WIN2_MST1			0x00d0
#define RK3368_WIN2_DSP_INFO1			0x00d4
#define RK3368_WIN2_DSP_ST1			0x00d8
#define RK3368_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3368_WIN2_MST2			0x00e0
#define RK3368_WIN2_DSP_INFO2			0x00e4
#define RK3368_WIN2_DSP_ST2			0x00e8
#define RK3368_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3368_WIN2_MST3			0x00f0
#define RK3368_WIN2_DSP_INFO3			0x00f4
#define RK3368_WIN2_DSP_ST3			0x00f8
#define RK3368_WIN2_FADING_CTRL			0x00fc
#define RK3368_WIN3_CTRL0			0x0100
#define RK3368_WIN3_CTRL1			0x0104
#define RK3368_WIN3_VIR0_1			0x0108
#define RK3368_WIN3_VIR2_3			0x010c
#define RK3368_WIN3_MST0			0x0110
#define RK3368_WIN3_DSP_INFO0			0x0114
#define RK3368_WIN3_DSP_ST0			0x0118
#define RK3368_WIN3_COLOR_KEY			0x011c
#define RK3368_WIN3_MST1			0x0120
#define RK3368_WIN3_DSP_INFO1			0x0124
#define RK3368_WIN3_DSP_ST1			0x0128
#define RK3368_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3368_WIN3_MST2			0x0130
#define RK3368_WIN3_DSP_INFO2			0x0134
#define RK3368_WIN3_DSP_ST2			0x0138
#define RK3368_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3368_WIN3_MST3			0x0140
#define RK3368_WIN3_DSP_INFO3			0x0144
#define RK3368_WIN3_DSP_ST3			0x0148
#define RK3368_WIN3_FADING_CTRL			0x014c
#define RK3368_HWC_CTRL0			0x0150
#define RK3368_HWC_CTRL1			0x0154
#define RK3368_HWC_MST				0x0158
#define RK3368_HWC_DSP_ST			0x015c
#define RK3368_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3368_HWC_DST_ALPHA_CTRL		0x0164
#define RK3368_HWC_FADING_CTRL			0x0168
#define RK3368_HWC_RESERVED1			0x016c
#define RK3368_POST_DSP_HACT_INFO		0x0170
#define RK3368_POST_DSP_VACT_INFO		0x0174
#define RK3368_POST_SCL_FACTOR_YRGB		0x0178
#define RK3368_POST_RESERVED			0x017c
#define RK3368_POST_SCL_CTRL			0x0180
#define RK3368_POST_DSP_VACT_INFO_F1		0x0184
#define RK3368_DSP_HTOTAL_HS_END		0x0188
#define RK3368_DSP_HACT_ST_END			0x018c
#define RK3368_DSP_VTOTAL_VS_END		0x0190
#define RK3368_DSP_VACT_ST_END			0x0194
#define RK3368_DSP_VS_ST_END_F1			0x0198
#define RK3368_DSP_VACT_ST_END_F1		0x019c
#define RK3368_PWM_CTRL				0x01a0
#define RK3368_PWM_PERIOD_HPR			0x01a4
#define RK3368_PWM_DUTY_LPR			0x01a8
#define RK3368_PWM_CNT				0x01ac
#define RK3368_BCSH_COLOR_BAR			0x01b0
#define RK3368_BCSH_BCS				0x01b4
#define RK3368_BCSH_H				0x01b8
#define RK3368_BCSH_CTRL			0x01bc
#define RK3368_CABC_CTRL0			0x01c0
#define RK3368_CABC_CTRL1			0x01c4
#define RK3368_CABC_CTRL2			0x01c8
#define RK3368_CABC_CTRL3			0x01cc
#define RK3368_CABC_GAUSS_LINE0_0		0x01d0
#define RK3368_CABC_GAUSS_LINE0_1		0x01d4
#define RK3368_CABC_GAUSS_LINE1_0		0x01d8
#define RK3368_CABC_GAUSS_LINE1_1		0x01dc
#define RK3368_CABC_GAUSS_LINE2_0		0x01e0
#define RK3368_CABC_GAUSS_LINE2_1		0x01e4
#define RK3368_FRC_LOWER01_0			0x01e8
#define RK3368_FRC_LOWER01_1			0x01ec
#define RK3368_FRC_LOWER10_0			0x01f0
#define RK3368_FRC_LOWER10_1			0x01f4
#define RK3368_FRC_LOWER11_0			0x01f8
#define RK3368_FRC_LOWER11_1			0x01fc
#define RK3368_IFBDC_CTRL			0x0200
#define RK3368_IFBDC_TILES_NUM			0x0204
#define RK3368_IFBDC_FRAME_RST_CYCLE		0x0208
#define RK3368_IFBDC_BASE_ADDR			0x020c
#define RK3368_IFBDC_MB_SIZE			0x0210
#define RK3368_IFBDC_CMP_INDEX_INIT		0x0214
#define RK3368_IFBDC_VIR			0x0220
#define RK3368_IFBDC_DEBUG0			0x0230
#define RK3368_IFBDC_DEBUG1			0x0234
#define RK3368_LATENCY_CTRL0			0x0250
#define RK3368_RD_MAX_LATENCY_NUM0		0x0254
#define RK3368_RD_LATENCY_THR_NUM0		0x0258
#define RK3368_RD_LATENCY_SAMP_NUM0		0x025c
#define RK3368_WIN0_DSP_BG			0x0260
#define RK3368_WIN1_DSP_BG			0x0264
#define RK3368_WIN2_DSP_BG			0x0268
#define RK3368_WIN3_DSP_BG			0x026c
#define RK3368_SCAN_LINE_NUM			0x0270
#define RK3368_CABC_DEBUG0			0x0274
#define RK3368_CABC_DEBUG1			0x0278
#define RK3368_CABC_DEBUG2			0x027c
#define RK3368_DBG_REG_000			0x0280
#define RK3368_DBG_REG_001			0x0284
#define RK3368_DBG_REG_002			0x0288
#define RK3368_DBG_REG_003			0x028c
#define RK3368_DBG_REG_004			0x0290
#define RK3368_DBG_REG_005			0x0294
#define RK3368_DBG_REG_006			0x0298
#define RK3368_DBG_REG_007			0x029c
#define RK3368_DBG_REG_008			0x02a0
#define RK3368_DBG_REG_016			0x02c0
#define RK3368_DBG_REG_017			0x02c4
#define RK3368_DBG_REG_018			0x02c8
#define RK3368_DBG_REG_019			0x02cc
#define RK3368_DBG_REG_020			0x02d0
#define RK3368_DBG_REG_021			0x02d4
#define RK3368_DBG_REG_022			0x02d8
#define RK3368_DBG_REG_023			0x02dc
#define RK3368_DBG_REG_028			0x02f0
#define RK3368_MMU_DTE_ADDR			0x0300
#define RK3368_MMU_STATUS			0x0304
#define RK3368_MMU_COMMAND			0x0308
#define RK3368_MMU_PAGE_FAULT_ADDR		0x030c
#define RK3368_MMU_ZAP_ONE_LINE			0x0310
#define RK3368_MMU_INT_RAWSTAT			0x0314
#define RK3368_MMU_INT_CLEAR			0x0318
#define RK3368_MMU_INT_MASK			0x031c
#define RK3368_MMU_INT_STATUS			0x0320
#define RK3368_MMU_AUTO_GATING			0x0324
#define RK3368_WIN2_LUT_ADDR			0x0400
#define RK3368_WIN3_LUT_ADDR			0x0800
#define RK3368_HWC_LUT_ADDR			0x0c00
#define RK3368_GAMMA_LUT_ADDR			0x1000
#define RK3368_CABC_GAMMA_LUT_ADDR		0x1800
#define RK3368_MCU_BYPASS_WPORT			0x2200
#define RK3368_MCU_BYPASS_RPORT			0x2300
/* rk3368 register definition end */

#define RK3366_REG_CFG_DONE			0x0000
#define RK3366_VERSION_INFO			0x0004
#define RK3366_SYS_CTRL				0x0008
#define RK3366_SYS_CTRL1			0x000c
#define RK3366_DSP_CTRL0			0x0010
#define RK3366_DSP_CTRL1			0x0014
#define RK3366_DSP_BG				0x0018
#define RK3366_MCU_CTRL				0x001c
#define RK3366_WB_CTRL0				0x0020
#define RK3366_WB_CTRL1				0x0024
#define RK3366_WB_YRGB_MST			0x0028
#define RK3366_WB_CBR_MST			0x002c
#define RK3366_WIN0_CTRL0			0x0030
#define RK3366_WIN0_CTRL1			0x0034
#define RK3366_WIN0_COLOR_KEY			0x0038
#define RK3366_WIN0_VIR				0x003c
#define RK3366_WIN0_YRGB_MST			0x0040
#define RK3366_WIN0_CBR_MST			0x0044
#define RK3366_WIN0_ACT_INFO			0x0048
#define RK3366_WIN0_DSP_INFO			0x004c
#define RK3366_WIN0_DSP_ST			0x0050
#define RK3366_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3366_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3366_WIN0_SCL_OFFSET			0x005c
#define RK3366_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3366_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3366_WIN0_FADING_CTRL			0x0068
#define RK3366_WIN0_CTRL2			0x006c
#define RK3366_WIN1_CTRL0			0x0070
#define RK3366_WIN1_CTRL1			0x0074
#define RK3366_WIN1_COLOR_KEY			0x0078
#define RK3366_WIN1_VIR				0x007c
#define RK3366_WIN1_YRGB_MST			0x0080
#define RK3366_WIN1_CBR_MST			0x0084
#define RK3366_WIN1_ACT_INFO			0x0088
#define RK3366_WIN1_DSP_INFO			0x008c
#define RK3366_WIN1_DSP_ST			0x0090
#define RK3366_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3366_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3366_WIN1_SCL_OFFSET			0x009c
#define RK3366_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3366_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3366_WIN1_FADING_CTRL			0x00a8
#define RK3366_WIN1_CTRL2			0x00ac
#define RK3366_WIN2_CTRL0			0x00b0
#define RK3366_WIN2_CTRL1			0x00b4
#define RK3366_WIN2_VIR0_1			0x00b8
#define RK3366_WIN2_VIR2_3			0x00bc
#define RK3366_WIN2_MST0			0x00c0
#define RK3366_WIN2_DSP_INFO0			0x00c4