path: root/drivers/hwmon/nct7904.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * nct7904.c - driver for Nuvoton NCT7904D.
 *
 * Copyright (c) 2015 Kontron
 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
 *
 * Copyright (c) 2019 Advantech
 * Author: Amy.Shih <amy.shih@advantech.com.tw>
 *
 * Copyright (c) 2020 Advantech
 * Author: Yuechao Zhao <yuechao.zhao@advantech.com.cn>
 *
 * Supports the following chips:
 *
 * Chip        #vin  #fan  #pwm  #temp  #dts  chip ID
 * nct7904d     20    12    4     5      8    0xc5
 */

#include <linux/module.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/hwmon.h>
#include <linux/watchdog.h>

#define VENDOR_ID_REG		0x7A	/* Any bank */
#define NUVOTON_ID		0x50
#define CHIP_ID_REG		0x7B	/* Any bank */
#define NCT7904_ID		0xC5
#define DEVICE_ID_REG		0x7C	/* Any bank */

#define BANK_SEL_REG		0xFF
#define BANK_0			0x00
#define BANK_1			0x01
#define BANK_2			0x02
#define BANK_3			0x03
#define BANK_4			0x04
#define BANK_MAX		0x04

#define FANIN_MAX		12	/* Counted from 1 */
#define VSEN_MAX		21	/* VSEN1..14, 3VDD, VBAT, V3VSB,
					   LTD (not a voltage), VSEN17..19 */
#define FANCTL_MAX		4	/* Counted from 1 */
#define TCPU_MAX		8	/* Counted from 1 */
#define TEMP_MAX		4	/* Counted from 1 */
#define SMI_STS_MAX		10	/* Counted from 1 */

#define VT_ADC_CTRL0_REG	0x20	/* Bank 0 */
#define VT_ADC_CTRL1_REG	0x21	/* Bank 0 */
#define VT_ADC_CTRL2_REG	0x22	/* Bank 0 */
#define FANIN_CTRL0_REG		0x24
#define FANIN_CTRL1_REG		0x25
#define DTS_T_CTRL0_REG		0x26
#define DTS_T_CTRL1_REG		0x27
#define VT_ADC_MD_REG		0x2E

#define VSEN1_HV_LL_REG		0x02	/* Bank 1; 2 regs (HV/LV) per sensor */
#define VSEN1_LV_LL_REG		0x03	/* Bank 1; 2 regs (HV/LV) per sensor */
#define VSEN1_HV_HL_REG		0x00	/* Bank 1; 2 regs (HV/LV) per sensor */
#define VSEN1_LV_HL_REG		0x01	/* Bank 1; 2 regs (HV/LV) per sensor */
#define SMI_STS1_REG		0xC1	/* Bank 0; SMI Status Register */
#define SMI_STS3_REG		0xC3	/* Bank 0; SMI Status Register */
#define SMI_STS5_REG		0xC5	/* Bank 0; SMI Status Register */
#define SMI_STS7_REG		0xC7	/* Bank 0; SMI Status Register */
#define SMI_STS8_REG		0xC8	/* Bank 0; SMI Status Register */

#define VSEN1_HV_REG		0x40	/* Bank 0; 2 regs (HV/LV) per sensor */
#define TEMP_CH1_HV_REG		0x42	/* Bank 0; same as VSEN2_HV */
#define LTD_HV_REG		0x62	/* Bank 0; 2 regs in VSEN range */
#define LTD_HV_HL_REG		0x44	/* Bank 1; 1 reg for LTD */
#define LTD_LV_HL_REG		0x45	/* Bank 1; 1 reg for LTD */
#define LTD_HV_LL_REG		0x46	/* Bank 1; 1 reg for LTD */
#define LTD_LV_LL_REG		0x47	/* Bank 1; 1 reg for LTD */
#define TEMP_CH1_CH_REG		0x05	/* Bank 1; 1 reg for LTD */
#define TEMP_CH1_W_REG		0x06	/* Bank 1; 1 reg for LTD */
#define TEMP_CH1_WH_REG		0x07	/* Bank 1; 1 reg for LTD */
#define TEMP_CH1_C_REG		0x04	/* Bank 1; 1 reg per sensor */
#define DTS_T_CPU1_C_REG	0x90	/* Bank 1; 1 reg per sensor */
#define DTS_T_CPU1_CH_REG	0x91	/* Bank 1; 1 reg per sensor */
#define DTS_T_CPU1_W_REG	0x92	/* Bank 1; 1 reg per sensor */
#define DTS_T_CPU1_WH_REG	0x93	/* Bank 1; 1 reg per sensor */
#define FANIN1_HV_REG		0x80	/* Bank 0; 2 regs (HV/LV) per sensor */
#define FANIN1_HV_HL_REG	0x60	/* Bank 1; 2 regs (HV/LV) per sensor */
#define FANIN1_LV_HL_REG	0x61	/* Bank 1; 2 regs (HV/LV) per sensor */
#define T_CPU1_HV_REG		0xA0	/* Bank 0; 2 regs (HV/LV) per sensor */

#define PRTS_REG		0x03	/* Bank 2 */
#define PFE_REG			0x00	/* Bank 2; PECI Function Enable */
#define TSI_CTRL_REG		0x50	/* Bank 2; TSI Control Register */
#define FANCTL1_FMR_REG		0x00	/* Bank 3; 1 reg per channel */
#define FANCTL1_OUT_REG		0x10	/* Bank 3; 1 reg per channel */

#define WDT_LOCK_REG		0xE0	/* W/O Lock Watchdog Register */
#define WDT_EN_REG		0xE1	/* R/O Watchdog Enable Register */
#define WDT_STS_REG		0xE2	/* R/O Watchdog Status Register */
#define WDT_TIMER_REG		0xE3	/* R/W Watchdog Timer Register */
#define WDT_SOFT_EN		0x55	/* Enable soft watchdog timer */
#define WDT_SOFT_DIS		0xAA	/* Disable soft watchdog timer */

#define VOLT_MONITOR_MODE	0x0
#define THERMAL_DIODE_MODE	0x1
#define THERMISTOR_MODE		0x3

#define ENABLE_TSI	BIT(1)

#define WATCHDOG_TIMEOUT	1	/* 1 minute default timeout */

/*The timeout range is 1-255 minutes*/
#define MIN_TIMEOUT		(1 * 60)
#define MAX_TIMEOUT		(255 * 60)

static int timeout;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes. 1 <= timeout <= 255, default="
			__MODULE_STRING(WATCHDOG_TIMEOUT) ".");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static const unsigned short normal_i2c[] = {
	0x2d, 0x2e, I2C_CLIENT_END
};

struct nct7904_data {
	struct i2c_client *client;
	struct watchdog_device wdt;
	struct mutex bank_lock;
	int bank_sel;
	u32 fanin_mask;
	u32 vsen_mask;
	u32 tcpu_mask;
	u8 fan_mode[FANCTL_MAX];
	u8 enable_dts;
	u8 has_dts;
	u8 temp_mode; /* 0: TR mode, 1: TD mode */
	u8 fan_alarm[2];
	u8 vsen_alarm[3];
};

/* Access functions */
static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
{
	int ret;

	mutex_lock(&data->bank_lock);
	if (data->bank_sel == bank)
		return 0;
	ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
	if (ret == 0)
		data->bank_sel = bank;
	else
		data->bank_sel = -1;
	return ret;
}

static inline void nct7904_bank_release(struct nct7904_data *data)
{
	mutex_unlock(&data->bank_lock);
}

/* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
static int nct7904_read_reg(struct nct7904_data *data,
			    unsigned int bank, unsigned int reg)
{
	struct i2c_client *client = data->