path: root/drivers/hwtracing/coresight/coresight-etm4x.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 */

#ifndef _CORESIGHT_CORESIGHT_ETM_H
#define _CORESIGHT_CORESIGHT_ETM_H

#include <asm/local.h>
#include <linux/const.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include "coresight-priv.h"

/*
 * Device registers:
 * 0x000 - 0x2FC: Trace		registers
 * 0x300 - 0x314: Management	registers
 * 0x318 - 0xEFC: Trace		registers
 * 0xF00: Management		registers
 * 0xFA0 - 0xFA4: Trace		registers
 * 0xFA8 - 0xFFC: Management	registers
 */
/* Trace registers (0x000-0x2FC) */
/* Main control and configuration registers */
#define TRCPRGCTLR			0x004
#define TRCPROCSELR			0x008
#define TRCSTATR			0x00C
#define TRCCONFIGR			0x010
#define TRCAUXCTLR			0x018
#define TRCEVENTCTL0R			0x020
#define TRCEVENTCTL1R			0x024
#define TRCRSR				0x028
#define TRCSTALLCTLR			0x02C
#define TRCTSCTLR			0x030
#define TRCSYNCPR			0x034
#define TRCCCCTLR			0x038
#define TRCBBCTLR			0x03C
#define TRCTRACEIDR			0x040
#define TRCQCTLR			0x044
/* Filtering control registers */
#define TRCVICTLR			0x080
#define TRCVIIECTLR			0x084
#define TRCVISSCTLR			0x088
#define TRCVIPCSSCTLR			0x08C
/* Derived resources registers */
#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */
#define TRCSEQRSTEVR			0x118
#define TRCSEQSTR			0x11C
#define TRCEXTINSELR			0x120
#define TRCEXTINSELRn(n)		(0x120 + (n * 4)) /* n = 0-3 */
#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
/* ID registers */
#define TRCIDR8				0x180
#define TRCIDR9				0x184
#define TRCIDR10			0x188
#define TRCIDR11			0x18C
#define TRCIDR12			0x190
#define TRCIDR13			0x194
#define TRCIMSPEC0			0x1C0
#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */
#define TRCIDR0				0x1E0
#define TRCIDR1				0x1E4
#define TRCIDR2				0x1E8
#define TRCIDR3				0x1EC
#define TRCIDR4				0x1F0
#define TRCIDR5				0x1F4
#define TRCIDR6				0x1F8
#define TRCIDR7				0x1FC
/*
 * Resource selection registers, n = 2-31.
 * First pair (regs 0, 1) is always present and is reserved.
 */
#define TRCRSCTLRn(n)			(0x200 + (n * 4))
/* Single-shot comparator registers, n = 0-7 */
#define TRCSSCCRn(n)			(0x280 + (n * 4))
#define TRCSSCSRn(n)			(0x2A0 + (n * 4))
#define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
/* Management registers (0x300-0x314) */
#define TRCOSLAR			0x300
#define TRCOSLSR			0x304
#define TRCPDCR				0x310
#define TRCPDSR				0x314
/* Trace registers (0x318-0xEFC) */
/* Address Comparator registers n = 0-15 */
#define TRCACVRn(n)			(0x400 + (n * 8))
#define TRCACATRn(n)			(0x480 + (n * 8))
/* ContextID/Virtual ContextID comparators, n = 0-7 */
#define TRCCIDCVRn(n)			(0x600 + (n * 8))
#define TRCVMIDCVRn(n)			(0x640 + (n * 8))
#define TRCCIDCCTLR0			0x680
#define TRCCIDCCTLR1			0x684
#define TRCVMIDCCTLR0			0x688
#define TRCVMIDCCTLR1			0x68C
/* Management register (0xF00) */
/* Integration control registers */
#define TRCITCTRL			0xF00
/* Trace registers (0xFA0-0xFA4) */
/* Claim tag registers */
#define TRCCLAIMSET			0xFA0
#define TRCCLAIMCLR			0xFA4
/* Management registers (0xFA8-0xFFC) */
#define TRCDEVAFF0			0xFA8
#define TRCDEVAFF1			0xFAC
#define TRCLAR				0xFB0
#define TRCLSR				0xFB4
#define TRCAUTHSTATUS			0xFB8
#define TRCDEVARCH			0xFBC
#define TRCDEVID			0xFC8
#define TRCDEVTYPE			0xFCC
#define TRCPIDR4			0xFD0
#define TRCPIDR5			0xFD4
#define TRCPIDR6			0xFD8
#define TRCPIDR7			0xFDC
#define TRCPIDR0			0xFE0
#define TRCPIDR1			0xFE4
#define TRCPIDR2			0xFE8
#define TRCPIDR3			0xFEC
#define TRCCIDR0			0xFF0
#define TRCCIDR1			0xFF4
#define TRCCIDR2			0xFF8
#define TRCCIDR3			0xFFC

#define TRCRSR_TA			BIT(12)

/*
 * Bit positions of registers that are defined above, in the sysreg.h style
 * of _MASK for multi bit fields and BIT() for single bits.
 */
#define TRCIDR0_INSTP0_MASK			GENMASK(2, 1)
#define TRCIDR0_TRCBB				BIT(5)
#define TRCIDR0_TRCCOND				BIT(6)
#define TRCIDR0_TRCCCI				BIT(7)
#define TRCIDR0_RETSTACK			BIT(9)
#define TRCIDR0_NUMEVENT_MASK			GENMASK(11, 10)
#define TRCIDR0_QFILT				BIT(14)
#define TRCIDR0_QSUPP_MASK			GENMASK(16, 15)
#define TRCIDR0_TSSIZE_MASK			GENMASK(28, 24)

#define TRCIDR2_CIDSIZE_MASK			GENMASK(9, 5)
#define TRCIDR2_VMIDSIZE_MASK			GENMASK(14, 10)
#define TRCIDR2_CCSIZE_MASK			GENMASK(28, 25)

#define TRCIDR3_CCITMIN_MASK			GENMASK(11, 0)
#define TRCIDR3_EXLEVEL_S_MASK			GENMASK(19, 16)
#define TRCIDR3_EXLEVEL_NS_MASK			GENMASK(23, 20)
#define TRCIDR3_TRCERR				BIT(24)
#define TRCIDR3_SYNCPR				BIT(25)
#define TRCIDR3_STALLCTL			BIT(26)
#define TRCIDR3_SYSSTALL			BIT(27)
#define TRCIDR3_NUMPROC_LO_MASK			GENMASK(30, 28)
#define TRCIDR3_NUMPROC_HI_MASK			GENMASK(13, 12)
#define TRCIDR3_NOOVERFLOW			BIT(31)

#define TRCIDR4_NUMACPAIRS_MASK			GENMASK(3, 0)
#define TRCIDR4_NUMPC_MASK			GENMASK(15, 12)
#define TRCIDR4_NUMRSPAIR_MASK			GENMASK(19, 16)
#define TRCIDR4_NUMSSCC_MASK			GENMASK(23, 20)
#define TRCIDR4_NUMCIDC_MASK			GENMASK(27, 24)
#define TRCIDR4_NUMVMIDC_MASK			GENMASK(31, 28)

#define TRCIDR5_NUMEXTIN_MASK			GENMASK(8, 0)
#define TRCIDR5_TRACEIDSIZE_MASK		GENMASK(21, 16)
#define TRCIDR5_ATBTRIG				BIT(22)
#define TRCIDR5_LPOVERRIDE			BIT(23)
#define TRCIDR5_NUMSEQSTATE_MASK		GENMASK(27, 25)
#define TRCIDR5_NUMCNTR_MASK			GENMASK(30, 28)

#define TRCCONFIGR_INSTP0_LOAD			BIT(1)
#define TRCCONFIGR_INSTP0_STORE			BIT(2)
#define TRCCONFIGR_INSTP0_LOAD_STORE		(TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
#define TRCCONFIGR_BB				BIT(3)
#define TRCCONFIGR_CCI				BIT(4)
#define TRCCONFIGR_CID				BIT(6)
#define TRCCONFIGR_VMID				BIT(7)
#define TRCCONFIGR_COND_MASK			GENMASK(10, 8)
#define TRCCONFIGR_TS				BIT(11)
#define TRCCONFIGR_RS				BIT(12)
#define TRCCONFIGR_QE_W_COUNTS			BIT(13)
#define TRCCONFIGR_QE_WO_COUNTS			BIT(14)
#define TRCCONFIGR_VMIDOPT			BIT(15)
#define TRCCONFIGR_DA				BIT(16)
#define TRCCONFIGR_DV				BIT(17)

#define TRCEVENTCTL1R_INSTEN_MASK		GENMASK(3, 0)
#define TRCEVENTCTL1R_INSTEN_0			BIT(0)
#define TRCEVENTCTL1R_INSTEN_1			BIT(1)
#define TRCEVENTCTL1R_INSTEN_2			BIT(2)
#define TRCEVENTCTL1R_INSTEN_3			BIT(3)
#define TRCEVENTCTL1R_ATB			BIT(11)
#define TRCEVENTCTL1R_LPOVERRIDE		BIT(12)

#define TRCSTALLCTLR_ISTALL			BIT(8)
#define TRCSTALLCTLR_INSTPRIORITY		BIT(10)
#define TRCSTALLCTLR_NOOVERFLOW			BIT(13)

#define TRCVICTLR_EVENT_MASK			GENMASK(7, 0)
#define TRCVICTLR_SSSTATUS			BIT(9)
#define TRCVICTLR_TRCRESET			BIT(10)
#define TRCVICTLR_TRCERR			BIT(11)
#define TRCVICTLR_EXLEVEL_MASK			GENMASK(22, 16)
#define TRCVICTLR_EXLEVEL_S_MASK		GENMASK(19, 16)
#define TRCVICTLR_EXLEVEL_NS_MASK		GENMASK(22, 20)

#define TRCACATRn_TYPE_MASK			GENMASK(1, 0)
#define TRCACATRn_CONTEXTTYPE_MASK		GENMASK(3, 2)
#define TRCACATRn_CONTEXTTYPE_CTXID		BIT(2)
#define TRCACATRn_CONTEXTTYPE_VMID		BIT(3)
#define TRCACATRn_CONTEXT_MASK			GENMASK(6, 4)
#define TRCACATRn_EXLEVEL_MASK			GENMASK(14, 8)

#define TRCSSCSRn_STATUS			BIT(31)
#define TRCSSCCRn_SAC_ARC_RST_MASK		GENMASK(24, 0)

#define TRCSSPCICRn_PC_MASK			GENMASK(7, 0)

#define TRCBBCTLR_MODE				BIT(8)
#define TRCBBCTLR_RANGE_MASK			GENMASK(7, 0)

#define TRCRSCTLRn_PAIRINV			BIT(21)
#define TRCRSCTLRn_INV				BIT(20)
#define TRCRSCTLRn_GROUP_MASK			GENMASK(19, 16)
#define TRCRSCTLRn_SELECT_MASK			GENMASK(15, 0)

/*
 * System instructions to access ETM registers.
 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
 */
#define ETM4x_OFFSET_TO_REG(x)		((x) >> 2)

#define ETM4x_CRn(n)			(((n) >> 7) & 0x7)
#define ETM4x_Op2(n)			(((n) >> 4) & 0x7)
#define ETM4x_CRm(n)			((n) & 0xf)

#include <asm/sysreg.h>
#define ETM4x_REG_NUM_TO_SYSREG(n)				\
	sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))

#define READ_ETM4x_REG(reg)					\
	read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
#define WRITE_ETM4x_REG(val, reg)				\
	write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))

#define read_etm4x_sysreg_const_offset(offset)			\
	READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))

#define write_etm4x_sysreg_const_offset(val, offset)		\
	WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))

#define CASE_READ(res, x)					\
	case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }

#define CASE_WRITE(val, x)					\
	case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }

#define CASE_NOP(__unused, x)					\
	case (x):	/* fall through */

#define ETE_ONLY_SYSREG_LIST(op, val)		\
	CASE_##op((val), TRCRSR)		\
	CASE_##op((val), TRCEXTINSELRn(1))	\
	CASE_##op((val), TRCEXTINSELRn(2))	\
	CASE_##op((val), TRCEXTINSELRn(3))

/* List of registers accessible via System instructions */
#define ETM4x_ONLY_SYSREG_LIST(op, val)		\
	CASE_##op((val), TRCPROCSELR)		\
	CASE_##op((val), TRCOSLAR)

#define ETM_COMMON_SYSREG_LIST(op, val)		\
	CASE_##op((val), TRCPRGCTLR)		\
	CASE_##op((val), TRCSTATR)		\
	CASE_##op((val), TRCCONFIGR)		\
	CASE_##op((val), TRCAUXCTLR)		\
	CASE_##op((val), TRCEVENTCTL0R)		\
	CASE_##op((val), TRCEVENTCTL1R)		\
	CASE_##op((val), TRCSTALLCTLR)		\
	CASE_##op((val), TRCTSCTLR)		\
	CASE_##op((val), TRCSYNCPR)		\
	CASE_##op((val), TRCCCCTLR)		\
	CASE_##op((val), TRCBBCTLR)		\
	CASE_##op((val), TRCTRACEIDR)		\
	CASE_##op((val), TRCQCTLR)		\
	CASE_##op((val), TRCVICTLR)		\
	CASE_##op((val), TRCVIIECTLR)		\
	CASE_##op((val), TRCVISSCTLR)		\
	CASE_##op((val), TRCVIPCSSCTLR)		\
	CASE_##op((val), TRCSEQEVRn(0))		\
	CASE_##op((val), TRCSEQEVRn(1))		\
	CASE_##op((val), TRCSEQEVRn(2))		\
	CASE_##op((val), TRCSEQRSTEVR)		\
	CASE_##op((val), TRCSEQSTR)		\
	CASE_##op((val), TRCEXTINSELR)		\
	CASE_##op((val), TRCCNTRLDVRn(0))	\
	CASE_##op((val), TRCCNTRLDVRn(1))	\
	CASE_##op((val), TRCCNTRLDVRn(2))	\
	CASE_##op((val), TRCCNTRLDVRn(3))	\
	CASE_##op((val), TRCCNTCTLRn(0))	\
	CASE_##op((val), TRCCNTCTLRn(1))	\
	CASE_##op((val), TRCCNTCTLRn(2))	\
	CASE_##op((val), TRCCNTCTLRn(3))	\
	CASE_##op((val), TRCCNTVRn(0))		\
	CASE_##op((val), TRCCNTVRn(1))		\
	CASE_##op((val), TRCCNTVRn(2))		\
	CASE_##op((val), TRCCNTVRn(3))		\
	CASE_##op((val), TRCIDR8)		\
	CASE_##op((val), TRCIDR9)		\
	CASE_##op((val), TRCIDR10)		\
	CASE_##op((val), TRCIDR11)		\
	CASE_##op((val), TRCIDR12)		\
	CASE_##op((val), TRCIDR13)		\
	CASE_##op((val), TRCIMSPECn(0))		\
	CASE_##op((val), TRCIMSPECn(1))		\
	CASE_##op((val), TRCIMSPECn(2))		\
	CASE_##op((val), TRCIMSPECn(3))		\
	CASE_##op((val), TRCIMSPECn(4))		\
	CASE_##op((val), TRCIMSPECn(5))		\
	CASE_##op((val), TRCIMSPECn(6))		\
	CASE_##op((val), TRCIMSPECn(7))		\
	CASE_##op((val), TRCIDR0)		\
	CASE_##op((val), TRCIDR1)		\
	CASE_##op((val), TRCIDR2)		\
	CASE_##op((val), TRCIDR3)		\
	CASE_##op((val), TRCIDR4)		\
	CASE_##op((val), TRCIDR5)		\
	CASE_##op((val), TRCIDR6)		\
	CASE_##op((val), TRCIDR7)		\
	CASE_##op((val), TRCRSCTLRn(2))		\
	CASE_##op((val), TRCRSCTLRn(3))		\
	CASE_##op((val), TRCRSCTLRn(4))		\
	CASE_##op((val), TRCRSCTLRn(5))		\
	CASE_##op((val), TRCRSCTLRn(6))		\
	CASE_##op((val), TRCRSCTLRn(7))		\
	CASE_##op((val), TRCRSCTLRn(8))		\
	CASE_##op((val), TRCRSCTLRn(9))		\
	CASE_##op((val), TRCRSCTLRn(10))	\
	CASE_##op((val), TRCRSCTLRn(11))	\
	CASE_##op((val), TRCRSCTLRn(12))	\
	CASE_##op((val), TRCRSCTLRn(13))	\
	CASE_##op((val), TRCRSCTLRn(14))	\
	CASE_##op((val), TRCRSCTLRn(15))	\
	CASE_##op((val), TRCRSCTLRn(16))	\
	CASE_##op((val), TRCRSCTLRn(17))	\
	CASE_##op((val), TRCRSCTLRn(18))	\
	CASE_##op((val), TRCRSCTLRn(19))	\
	CASE_##op((val), TRCRSCTLRn(20))	\
	CASE_##op((val), TRCRSCTLRn(21))	\
	CASE_##op((val), TRCRSCTLRn(22))	\
	CASE_##op((val), TRCRSCTLRn(23))	\
	CASE_##op((val), TRCRSCTLRn(24))	\
	CASE_##op((val), TRCRSCTLRn(25))	\
	CASE_##op((val), TRCRSCTLRn(26))	\
	CASE_##op((val), TRCRSCTLRn(27))	\
	CASE_##op((val), TRCRSCTLRn(28))	\
	CASE_##op((val), TRCRSCTLRn(29))	\
	CASE_##op((val), TR