path: root/drivers/i2c/busses/i2c-nomadik.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2009 ST-Ericsson SA
 * Copyright (C) 2009 STMicroelectronics
 *
 * I2C master mode controller driver, used in Nomadik 8815
 * and Ux500 platforms.
 *
 * The Mobileye EyeQ5 platform is also supported; it uses
 * the same Ux500/DB8500 IP block with two quirks:
 *  - The memory bus only supports 32-bit accesses.
 *  - A register must be configured for the I2C speed mode;
 *    it is located in a shared register region called OLB.
 *
 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
 * Author: Sachin Verma <sachin.verma@st.com>
 */
#include <linux/amba/bus.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define DRIVER_NAME "nmk-i2c"

/* I2C Controller register offsets */
#define I2C_CR		(0x000)
#define I2C_SCR		(0x004)
#define I2C_HSMCR	(0x008)
#define I2C_MCR		(0x00C)
#define I2C_TFR		(0x010)
#define I2C_SR		(0x014)
#define I2C_RFR		(0x018)
#define I2C_TFTR	(0x01C)
#define I2C_RFTR	(0x020)
#define I2C_DMAR	(0x024)
#define I2C_BRCR	(0x028)
#define I2C_IMSCR	(0x02C)
#define I2C_RISR	(0x030)
#define I2C_MISR	(0x034)
#define I2C_ICR		(0x038)

/* Control registers */
#define I2C_CR_PE		BIT(0)		/* Peripheral Enable */
#define I2C_CR_OM		GENMASK(2, 1)	/* Operating mode */
#define I2C_CR_SAM		BIT(3)		/* Slave addressing mode */
#define I2C_CR_SM		GENMASK(5, 4)	/* Speed mode */
#define I2C_CR_SGCM		BIT(6)		/* Slave general call mode */
#define I2C_CR_FTX		BIT(7)		/* Flush Transmit */
#define I2C_CR_FRX		BIT(8)		/* Flush Receive */
#define I2C_CR_DMA_TX_EN	BIT(9)		/* DMA Tx enable */
#define I2C_CR_DMA_RX_EN	BIT(10)		/* DMA Rx Enable */
#define I2C_CR_DMA_SLE		BIT(11)		/* DMA sync. logic enable */
#define I2C_CR_LM		BIT(12)		/* Loopback mode */
#define I2C_CR_FON		GENMASK(14, 13)	/* Filtering on */
#define I2C_CR_FS		GENMASK(16, 15)	/* Force stop enable */

/* Slave control register (SCR) */
#define I2C_SCR_SLSU		GENMASK(31, 16)	/* Slave data setup time */

/* Master controller (MCR) register */
#define I2C_MCR_OP		BIT(0)		/* Operation */
#define I2C_MCR_A7		GENMASK(7, 1)	/* 7-bit address */
#define I2C_MCR_EA10		GENMASK(10, 8)	/* 10-bit Extended address */
#define I2C_MCR_SB		BIT(11)		/* Extended address */
#define I2C_MCR_AM		GENMASK(13, 12)	/* Address type */
#define I2C_MCR_STOP		BIT(14)		/* Stop condition */
#define I2C_MCR_LENGTH		GENMASK(25, 15)	/* Transaction length */

/* Status register (SR) */
#define I2C_SR_OP		GENMASK(1, 0)	/* Operation */
#define I2C_SR_STATUS		GENMASK(3, 2)	/* controller status */
#define I2C_SR_CAUSE		GENMASK(6, 4)	/* Abort cause */
#define I2C_SR_TYPE		GENMASK(8, 7)	/* Receive type */
#define I2C_SR_LENGTH		GENMASK(19, 9)	/* Transfer length */

/* Baud-rate counter register (BRCR) */
#define I2C_BRCR_BRCNT1		GENMASK(31, 16)	/* Baud-rate counter 1 */
#define I2C_BRCR_BRCNT2		GENMASK(15, 0)	/* Baud-rate counter 2 */

/* Interrupt mask set/clear (IMSCR) bits */
#define I2C_IT_TXFE		BIT(0)
#define I2C_IT_TXFNE		BIT(1)
#define I2C_IT_TXFF		BIT(2)
#define I2C_IT_TXFOVR		BIT(3)
#define I2C_IT_RXFE		BIT(4)
#define I2C_IT_RXFNF		BIT(5)
#define I2C_IT_RXFF		BIT(6)
#define I2C_IT_RFSR		BIT(16)
#define I2C_IT_RFSE		BIT(17)
#define I2C_IT_WTSR		BIT(18)
#define I2C_IT_MTD		BIT(19)
#define I2C_IT_STD		BIT(20)
#define I2C_IT_MAL		BIT(24)
#define I2C_IT_BERR		BIT(25)
#define I2C_IT_MTDWS		BIT(28)

/* some bits in ICR are reserved */
#define I2C_CLEAR_ALL_INTS	0x131f007f

/* maximum threshold value */
#define MAX_I2C_FIFO_THRESHOLD	15

enum i2c_freq_mode {
	I2C_FREQ_MODE_STANDARD,		/* up to 100 Kb/s */
	I2C_FREQ_MODE_FAST,		/* up to 400 Kb/s */
	I2C_FREQ_MODE_HIGH_SPEED,	/* up to 3.4 Mb/s */
	I2C_FREQ_MODE_FAST_PLUS,	/* up to 1 Mb/s */
};

/* Mobileye EyeQ5 offset into a shared register region (called OLB) */
#define NMK_I2C_EYEQ5_OLB_IOCR2			0x0B8

enum i2c_eyeq5_speed {
	I2C_EYEQ5_SPEED_FAST,
	I2C_EYEQ5_SPEED_FAST_PLUS,
	I2C_EYEQ5_SPEED_HIGH_SPEED,
};

/**
 * struct i2c_vendor_data - per-vendor variations
 * @has_mtdws: variant has the MTDWS bit
 * @fifodepth: variant FIFO depth
 */
struct i2c_vendor_data {
	bool has_mtdws;
	u32 fifodepth;
};

enum i2c_status {
	I2C_NOP,
	I2C_ON_GOING,
	I2C_OK,
	I2C_ABORT
};

/* operation */
enum i2c_operation {
	I2C_NO_OPERATION = 0xff,
	I2C_WRITE = 0x00,
	I2C_READ = 0x01
};

enum i2c_operating_mode {
	I2C_OM_SLAVE,
	I2C_OM_MASTER,
	I2C_OM_MASTER_OR_SLAVE,
};

/**
 * struct i2c_nmk_client - client specific data
 * @slave_adr: 7-bit slave address
 * @count: no. bytes to be transferred
 * @buffer: client data buffer
 * @xfer_bytes: bytes transferred till now
 * @operation: current I2C operation
 */
struct i2c_nmk_client {
	unsigned short		slave_adr;
	unsigned long		count;
	unsigned char		*buffer;
	unsigned long		xfer_bytes;
	enum i2c_operation	operation;
};

/**
 * struct nmk_i2c_dev - private data structure of the controller.
 * @vendor: vendor data for this variant.
 * @adev: parent amba device.
 * @adap: corresponding I2C adapter.
 * @irq: interrupt line for the controller.
 * @virtbase: virtual io memory area.
 * @clk: hardware i2c block clock.
 * @cli: holder of client specific data.
 * @clk_freq: clock frequency for the operation mode
 * @tft: Tx FIFO Threshold in bytes
 * @rft: Rx FIFO Threshold in bytes
 * @timeout_usecs: Slave response timeout
 * @sm: speed mode
 * @stop: stop condition.
 * @xfer_wq: xfer done wait queue.
 * @xfer_done: xfer done boolean.
 * @result: controller propogated result.
 * @has_32b_bus: controller is on a bus that only supports 32-bit accesses.
 */
struct nmk_i2c_dev {
	struct i2c_vendor_data		*vendor;
	struct amba_device		*adev;
	struct i2c_adapter		adap;
	int				irq;
	void __iomem			*virtbase;
	struct clk			*clk;
	struct i2c_nmk_client		cli;
	u32				clk_freq;
	unsigned char			tft;
	unsigned char			rft;
	u32				timeout_usecs;
	enum