// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/i3c/master.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#define DEV_ID 0x0
#define DEV_ID_I3C_MASTER 0x5034
#define CONF_STATUS0 0x4
#define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
#define CONF_STATUS0_ECC_CHK BIT(28)
#define CONF_STATUS0_INTEG_CHK BIT(27)
#define CONF_STATUS0_CSR_DAP_CHK BIT(26)
#define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
#define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
#define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
#define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
#define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
#define CONF_STATUS0_SUPPORTS_DDR BIT(5)
#define CONF_STATUS0_SEC_MASTER BIT(4)
#define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
#define CONF_STATUS1 0x8
#define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
#define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
#define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
#define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
#define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
#define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
#define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
#define REV_ID 0xc
#define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
#define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
#define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
#define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
#define CTRL 0x10
#define CTRL_DEV_EN BIT(31)
#define CTRL_HALT_EN BIT(30)
#define CTRL_MCS BIT(29)
#define CTRL_MCS_EN BIT(28)
#define CTRL_HJ_DISEC BIT(8)
#define CTRL_MST_ACK BIT(7)
#define CTRL_HJ_ACK BIT(6)
#define CTRL_HJ_INIT BIT(5)
#define CTRL_MST_INIT BIT(4)
#define CTRL_AHDR_OPT BIT(3)
#define CTRL_PURE_BUS_MODE 0
#define CTRL_MIXED_FAST_BUS_MODE 2
#define CTRL_MIXED_SLOW_BUS_MODE 3
#define CTRL_BUS_MODE_MASK GENMASK(1, 0)
#define PRESCL_CTRL0 0x1
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