// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 Analog Devices, Inc.
* Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/sysfs.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mod_devicetable.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/unaligned.h>
#include "adxl367.h"
#define ADXL367_REG_DEVID 0x00
#define ADXL367_DEVID_AD 0xAD
#define ADXL367_REG_STATUS 0x0B
#define ADXL367_STATUS_INACT_MASK BIT(5)
#define ADXL367_STATUS_ACT_MASK BIT(4)
#define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
#define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
#define ADXL367_REG_X_DATA_H 0x0E
#define ADXL367_REG_Y_DATA_H 0x10
#define ADXL367_REG_Z_DATA_H 0x12
#define ADXL367_REG_TEMP_DATA_H 0x14
#define ADXL367_REG_EX_ADC_DATA_H 0x16
#define ADXL367_DATA_MASK GENMASK(15, 2)
#define ADXL367_TEMP_25C 165
#define ADXL367_TEMP_PER_C 54
#define ADXL367_VOLTAGE_OFFSET 8192
#define ADXL367_VOLTAGE_MAX_MV 1000
#define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
#define ADXL367_REG_RESET 0x1F
#define ADXL367_RESET_CODE 0x52
#define ADXL367_REG_THRESH_ACT_H 0x20
#define ADXL367_REG_THRESH_INACT_H 0x23
#define ADXL367_THRESH_MAX GENMASK(12, 0)
#define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
#define ADXL367_THRESH_H_MASK GENMASK(6, 0)
#define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
#define ADXL367_THRESH_L_MASK GENMASK(7, 2)
#define ADXL367_REG_TIME_ACT 0x22
#define ADXL367_REG_TIME_INACT_H 0x25
#define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
#define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
#define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
#define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
#define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
#define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
#define ADXL367_REG_ACT_INACT_CTL 0x27
#define ADXL367_ACT_EN_MASK GENMASK(1, 0)
#define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
#define ADXL367_REG_FIFO_CTL 0x28
#define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
#define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
#define ADXL367_REG_FIFO_SAMPLES 0x29
#define ADXL367_FIFO_SIZE 512
#define ADXL367_FIFO_MAX_WATERMARK 511
#define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
#define ADXL367_SAMPLES_H_MASK BIT(2)
#define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
#define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
#define ADXL367_REG_INT1_MAP 0x2A
#define ADXL367_INT_INACT_MASK BIT(5)
#define ADXL367_INT_ACT_MASK BIT(4)
#define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
#define ADXL367_REG_FILTER_CTL 0x2C
#define ADXL367_FILTER_CTL_
