path: root/drivers/iio/accel/adxl372.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * ADXL372 3-Axis Digital Accelerometer core driver
 *
 * Copyright 2018 Analog Devices Inc.
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include "adxl372.h"

/* ADXL372 registers definition */
#define ADXL372_DEVID			0x00
#define ADXL372_DEVID_MST		0x01
#define ADXL372_PARTID			0x02
#define ADXL372_STATUS_1		0x04
#define ADXL372_STATUS_2		0x05
#define ADXL372_FIFO_ENTRIES_2		0x06
#define ADXL372_FIFO_ENTRIES_1		0x07
#define ADXL372_X_DATA_H		0x08
#define ADXL372_X_DATA_L		0x09
#define ADXL372_Y_DATA_H		0x0A
#define ADXL372_Y_DATA_L		0x0B
#define ADXL372_Z_DATA_H		0x0C
#define ADXL372_Z_DATA_L		0x0D
#define ADXL372_X_MAXPEAK_H		0x15
#define ADXL372_X_MAXPEAK_L		0x16
#define ADXL372_Y_MAXPEAK_H		0x17
#define ADXL372_Y_MAXPEAK_L		0x18
#define ADXL372_Z_MAXPEAK_H		0x19
#define ADXL372_Z_MAXPEAK_L		0x1A
#define ADXL372_OFFSET_X		0x20
#define ADXL372_OFFSET_Y		0x21
#define ADXL372_OFFSET_Z		0x22
#define ADXL372_X_THRESH_ACT_H		0x23
#define ADXL372_X_THRESH_ACT_L		0x24
#define ADXL372_Y_THRESH_ACT_H		0x25
#define ADXL372_Y_THRESH_ACT_L		0x26
#define ADXL372_Z_THRESH_ACT_H		0x27
#define ADXL372_Z_THRESH_ACT_L		0x28
#define ADXL372_TIME_ACT		0x29
#define ADXL372_X_THRESH_INACT_H	0x2A
#define ADXL372_X_THRESH_INACT_L	0x2B
#define ADXL372_Y_THRESH_INACT_H	0x2C
#define ADXL372_Y_THRESH_INACT_L	0x2D
#define ADXL372_Z_THRESH_INACT_H	0x2E
#define ADXL372_Z_THRESH_INACT_L	0x2F
#define ADXL372_TIME_INACT_H		0x30
#define ADXL372_TIME_INACT_L		0x31
#define ADXL372_X_THRESH_ACT2_H		0x32
#define ADXL372_X_THRESH_ACT2_L		0x33
#define ADXL372_Y_THRESH_ACT2_H		0x34
#define ADXL372_Y_THRESH_ACT2_L		0x35
#define ADXL372_Z_THRESH_ACT2_H		0x36
#define ADXL372_Z_THRESH_ACT2_L		0x37
#define ADXL372_HPF			0x38
#define ADXL372_FIFO_SAMPLES		0x39
#define ADXL372_FIFO_CTL		0x3A
#define ADXL372_INT1_MAP		0x3B
#define ADXL372_INT2_MAP		0x3C
#define ADXL372_TIMING			0x3D
#define ADXL372_MEASURE			0x3E
#define ADXL372_POWER_CTL		0x3F
#define ADXL372_SELF_TEST		0x40
#define ADXL372_RESET			0x41
#define ADXL372_FIFO_DATA		0x42

#define ADXL372_DEVID_VAL		0xAD
#define ADXL372_PARTID_VAL		0xFA
#define ADXL372_RESET_CODE		0x52

/* ADXL372_POWER_CTL */
#define ADXL372_POWER_CTL_MODE_MSK		GENMASK_ULL(1, 0)
#define ADXL372_POWER_CTL_MODE(x)		(((x) & 0x3) << 0)

/* ADXL372_MEASURE */
#define ADXL372_MEASURE_LINKLOOP_MSK		GENMASK_ULL(5, 4)
#define ADXL372_MEASURE_LINKLOOP_MODE(x)	(((x) & 0x3) << 4)
#define ADXL372_MEASURE_BANDWIDTH_MSK		GENMASK_ULL(2, 0)
#define ADXL372_MEASURE_BANDWIDTH_MODE(x)	(((x) & 0x7) << 0)

/* ADXL372_TIMING */
#define ADXL372_TIMING_ODR_MSK			GENMASK_ULL(7, 5)
#define ADXL372_TIMING_ODR_MODE(x)		(((x) & 0x7) << 5)

/* ADXL372_FIFO_CTL */
#define ADXL372_FIFO_CTL_FORMAT_MSK		GENMASK(5, 3)
#define ADXL372_FIFO_CTL_FORMAT_MODE(x)		(((x) & 0x7) << 3)
#define ADXL372_FIFO_CTL_MODE_MSK		GENMASK(2, 1)
#define ADXL372_FIFO_CTL_MODE_MODE(x)		(((x) & 0x3) << 1)
#define ADXL372_FIFO_CTL_SAMPLES_MSK		BIT(1)
#define ADXL372_FIFO_CTL_SAMPLES_MODE(x)	(((x) > 0xFF) ? 1 : 0)

/* ADXL372_STATUS_1 */
#define ADXL372_STATUS_1_DATA_RDY(x)		(((x) >> 0) & 0x1)
#define ADXL372_STATUS_1_FIFO_RDY(x)		(((x) >> 1) & 0x1)
#define ADXL372_STATUS_1_FIFO_FULL(x)		(((x) >> 2) & 0x1)
#define ADXL372_STATUS_1_FIFO_OVR(x)		(((x) >> 3) & 0x1)
#define ADXL372_STATUS_1_USR_NVM_BUSY(x)	(((x) >> 5) & 0x1)
#define ADXL372_STATUS_1_AWAKE(x)		(((x) >> 6) & 0x1)
#define ADXL372_STATUS_1_ERR_USR_REGS(x)	(((x) >> 7) & 0x1)

/* ADXL372_STATUS_2 */
#define ADXL372_STATUS_2_INACT(x)		(((x) >> 4) & 0x1)
#define ADXL372_STATUS_2_ACT(x)			(((x) >> 5) & 0x1)
#define ADXL372_STATUS_2_AC2(x)			(((x) >> 6) & 0x1)

/* ADXL372_INT1_MAP */
#define ADXL372_INT1_MAP_DATA_RDY_MSK		BIT(0)
#define ADXL372_INT1_MAP_DATA_RDY_MODE(x)	(((x) & 0x1) << 0)
#define ADXL372_INT1_MAP_FIFO_RDY_MSK		BIT(1)
#define ADXL372_INT1_MAP_FIFO_RDY_MODE(x)	(((x) & 0x1) << 1)
#define ADXL372_INT1_MAP_FIFO_FULL_MSK		BIT(2)
#define ADXL372_INT1_MAP_FIFO_FULL_MODE(x)	(((x) & 0x1) << 2)
#define ADXL372_INT1_MAP_FIFO_OVR_MSK		BIT(3)
#define ADXL372_INT1_MAP_FIFO_OVR_MODE(x)	(((x) & 0x1) << 3)
#define ADXL372_INT1_MAP_INACT_MSK		BIT(4)
#define ADXL372_INT1_MAP_INACT_MODE(x)		(((x) & 0x1) << 4)
#define ADXL372_INT1_MAP_ACT_MSK		BIT(5)
#define ADXL372_INT1_MAP_ACT_MODE(x)		(((x) & 0x1) << 5)
#define ADXL372_INT1_MAP_AWAKE_MSK		BIT(6)
#define ADXL372_INT1_MAP_AWAKE_MODE(x)		(((x) & 0x1) << 6)
#define ADXL372_INT1_MAP_LOW_MSK		BIT(7)
#define ADXL372_INT1_MAP_LOW_MODE(x)		(((x) & 0x1) << 7)

/* ADX372_THRESH */
#define ADXL372_THRESH_VAL_H_MSK	GENMASK(10, 3)
#define ADXL372_THRESH_VAL_H_SEL(x)	FIELD_GET(ADXL372_THRESH_VAL_H_MSK, x)
#define ADXL372_THRESH_VAL_L_MSK	GENMASK(2, 0)
#define ADXL372_THRESH_VAL_L_SEL(x)	FIELD_GET(ADXL372_THRESH_VAL_L_MSK, x)

/* The ADXL372 includes a deep, 512 sample FIFO buffer */
#define ADXL372_FIFO_SIZE			512
#define ADXL372_X_AXIS_EN(x)			((x) & BIT(0))
#define ADXL372_Y_AXIS_EN(x)			((x) & BIT(1))
#define ADXL372_Z_AXIS_EN(x)			((x) & BIT(2))

/*
 * At +/- 200g with 12-bit resolution, scale is computed as:
 * (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
 */
#define ADXL372_USCALE	958241

enum adxl372_op_mode {
	ADXL372_STANDBY,
	ADXL372_WAKE_UP,
	ADXL372_INSTANT_ON,
	ADXL372_FULL_BW_MEASUREMENT,
};

enum adxl372_act_proc_mode {
	ADXL372_DEFAULT,
	ADXL372_LINKED,
	ADXL372_LOOPED,
};

enum adxl372_th_activity {
	ADXL372_ACTIVITY,
	ADXL372_ACTIVITY2,
	ADXL372_INACTIVITY,
};

enum adxl372_odr {
	ADXL372_ODR_400HZ,
	ADXL372_ODR_800HZ,
	ADXL372_ODR_1600HZ,
	ADXL372_ODR_3200HZ,
	ADXL372_ODR_6400HZ,
};

enum adxl372_bandwidth {
	ADXL372_BW_200HZ,
	ADXL372_BW_400HZ,
	ADXL372_BW_800HZ,
	ADXL372_BW_1600HZ,
	ADXL372_BW_3200HZ,
};

static const unsigned int adxl372_th_reg_high_addr[3] = {
	[ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H,
	[ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H,
	[ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H,
};

enum adxl372_fifo_format