path: root/drivers/iio/adc/ad4695.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips
 *
 * https://www.analog.com/en/products/ad4695.html
 * https://www.analog.com/en/products/ad4696.html
 * https://www.analog.com/en/products/ad4697.html
 * https://www.analog.com/en/products/ad4698.html
 *
 * Copyright 2024 Analog Devices Inc.
 * Copyright 2024 BayLibre, SAS
 */

#include <linux/align.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/minmax.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/units.h>

#include <dt-bindings/iio/adi,ad4695.h>

/* AD4695 registers */
#define AD4695_REG_SPI_CONFIG_A				0x0000
#define   AD4695_REG_SPI_CONFIG_A_SW_RST		  (BIT(7) | BIT(0))
#define   AD4695_REG_SPI_CONFIG_A_ADDR_DIR		  BIT(5)
#define AD4695_REG_SPI_CONFIG_B				0x0001
#define   AD4695_REG_SPI_CONFIG_B_INST_MODE		  BIT(7)
#define AD4695_REG_DEVICE_TYPE				0x0003
#define AD4695_REG_SCRATCH_PAD				0x000A
#define AD4695_REG_VENDOR_L				0x000C
#define AD4695_REG_VENDOR_H				0x000D
#define AD4695_REG_LOOP_MODE				0x000E
#define AD4695_REG_SPI_CONFIG_C				0x0010
#define   AD4695_REG_SPI_CONFIG_C_MB_STRICT		  BIT(7)
#define AD4695_REG_SPI_STATUS				0x0011
#define AD4695_REG_STATUS				0x0014
#define AD4695_REG_ALERT_STATUS1			0x0015
#define AD4695_REG_ALERT_STATUS2			0x0016
#define AD4695_REG_CLAMP_STATUS				0x001A
#define AD4695_REG_SETUP				0x0020
#define   AD4695_REG_SETUP_LDO_EN			  BIT(4)
#define   AD4695_REG_SETUP_SPI_MODE			  BIT(2)
#define   AD4695_REG_SETUP_SPI_CYC_CTRL			  BIT(1)
#define AD4695_REG_REF_CTRL				0x0021
#define   AD4695_REG_REF_CTRL_OV_MODE			  BIT(7)
#define   AD4695_REG_REF_CTRL_VREF_SET			  GENMASK(4, 2)
#define   AD4695_REG_REF_CTRL_REFHIZ_EN			  BIT(1)
#define   AD4695_REG_REF_CTRL_REFBUF_EN			  BIT(0)
#define AD4695_REG_SEQ_CTRL				0x0022
#define   AD4695_REG_SEQ_CTRL_STD_SEQ_EN		  BIT(7)
#define   AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS		  GENMASK(6, 0)
#define AD4695_REG_AC_CTRL				0x0023
#define AD4695_REG_STD_SEQ_CONFIG			0x0024
#define AD4695_REG_GPIO_CTRL				0x0026
#define AD4695_REG_GP_MODE				0x0027
#define AD4695_REG_TEMP_CTRL				0x0029
#define   AD4695_REG_TEMP_CTRL_TEMP_EN			  BIT(0)
#define AD4695_REG_CONFIG_IN(n)				(0x0030 | (n))
#define   AD4695_REG_CONFIG_IN_MODE			  BIT(6)
#define   AD4695_REG_CONFIG_IN_PAIR			  GENMASK(5, 4)
#define   AD4695_REG_CONFIG_IN_AINHIGHZ_EN		  BIT(3)
#define AD4695_REG_UPPER_IN(n)				(0x0040 | (2 * (n)))
#define AD4695_REG_LOWER_IN(n)				(0x0060 | (2 * (n)))
#define AD4695_REG_HYST_IN(n)				(0x0080 | (2 * (n)))
#define AD4695_REG_OFFSET_IN(n)				(0x00A0 | (2 * (n)))
#define AD4695_REG_GAIN_IN(n)				(0x00C0 | (2 * (n)))
#define AD4695_REG_AS_SLOT(n)				(0x0100 | (n))
#define   AD4695_REG_AS_SLOT_INX			  GENMASK(3, 0)

/* Conversion mode commands */
#define AD4695_CMD_EXIT_CNV_MODE	0x0A
#define AD4695_CMD_TEMP_CHAN		0x0F
#define AD4695_CMD_VOLTAGE_CHAN(n)	(0x10 | (n))

/* timing specs */
#define AD4695_T_CONVERT_NS		415
#define AD4695_T_WAKEUP_HW_MS		3
#define AD4695_T_WAKEUP_SW_MS		3
#define AD4695_T_REFBUF_MS		100
#define AD4695_T_REGCONFIG_NS		20
#define AD4695_REG_ACCESS_SCLK_HZ	(10 * MEGA)

/* Max number of voltage input channels. */
#define AD4695_MAX_CHANNELS		16
/* Max size of 1 raw sample in bytes. */
#define AD4695_MAX_CHANNEL_SIZE		2

enum ad4695_in_pair {
	AD4695_IN_PAIR_REFGND,
	AD4695_IN_PAIR_COM,
	AD4695_IN_PAIR_EVEN_ODD,
};

struct ad4695_chip_info {
	const char *name;
	int max_sample_rate;
	u32 t_acq_ns;
	u8 num_voltage_inputs;
};

struct ad4695_channel_config {
	unsigned int channel;
	bool highz_en;
	bool bipolar;
	enum ad4695_in_pair pin_pairing;
	unsigned int common_mode_mv;
};

struct ad4695_state {
	struct spi_device *spi;
	struct regmap *regmap;
	struct regmap *regmap16;
	struct gpio_desc *reset_gpio;
	/* voltages channels plus temperature and timestamp */
	struct iio_chan_spec iio_chan[AD4695_MAX_CHANNELS + 2];
	struct ad4695_channel_config channels_cfg[AD4695_MAX_CHANNELS];
	const struct ad4695_chip_info *chip_info;
	/* Reference voltage. */
	unsigned int vref_mv;
	/* Common mode input pin voltage. */
	unsigned int com_mv;
	/* 1 per voltage and temperature chan plus 1 xfer to trigger 1st CNV */
	struct spi_transfer buf_read_xfer[AD4695_MAX_CHANNELS + 2];
	struct spi_message buf_read_msg;
	/* Raw conversion data received. */
	u8 buf[ALIGN((AD4695_MAX_CHANNELS + 2) * AD4695_MAX_CHANNEL_SIZE,
		     sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
	u16 raw_data;
	/* Commands to send for single conversion. */
	u16 cnv_cmd;
	u8 cnv_cmd2;
};

static const struct regmap_range ad4695_regmap_rd_ranges[] = {
	regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
	regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE),
	regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
	regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE),
	regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
	regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2),
	regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS),
	regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),
	regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),
	regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),
	regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),
};

static const struct regmap_access_table ad4695_regmap_rd_table = {
	.yes_ranges = ad4695_regmap_rd_ranges,
	.n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges),
};

static const struct regmap_range ad4695_regmap_wr_ranges[] = {
	regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
	regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
	regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE),
	regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
	regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTR