// SPDX-License-Identifier: GPL-2.0+
/*
* IIO driver for MCP356X/MCP356XR and MCP346X/MCP346XR series ADC chip family
*
* Copyright (C) 2022-2023 Microchip Technology Inc. and its subsidiaries
*
* Author: Marius Cristea <marius.cristea@microchip.com>
*
* Datasheet for MCP3561, MCP3562, MCP3564 can be found here:
* https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf
* Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here:
* https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf
* Datasheet for MCP3461, MCP3462, MCP3464 can be found here:
* https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf
* Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here:
* https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf
*/
#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/units.h>
#include <linux/util_macros.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define MCP3564_ADCDATA_REG 0x00
#define MCP3564_CONFIG0_REG 0x01
#define MCP3564_CONFIG0_ADC_MODE_MASK GENMASK(1, 0)
/* Current Source/Sink Selection Bits for Sensor Bias */
#define MCP3564_CONFIG0_CS_SEL_MASK GENMASK(3, 2)
/* Internal clock is selected and AMCLK is present on the analog master clock output pin */
#define MCP3564_CONFIG0_USE_INT_CLK_OUTPUT_EN 0x03
/* Internal clock is selected and no clock output is present on the CLK pin */
#define MCP3564_CONFIG0_USE_INT_CLK 0x02
/* External digital clock */
#define MCP3564_CONFIG0_USE_EXT_CLK 0x01
/* External digital clock (default) */
#define MCP3564_CONFIG0_USE_EXT_CLK_DEFAULT 0x00
#define MCP3564_CONFIG0_CLK_SEL_MASK GENMASK(5, 4)
#define MCP3456_CONFIG0_BIT6_DEFAULT BIT(6)
#define MCP3456_CONFIG0_VREF_MASK BIT(7)
#define MCP3564_CONFIG1_REG 0x02
#define MCP3564_CONFIG1_OVERSPL_RATIO_MASK GENMASK(5, 2)
#define MCP3564_CONFIG2_REG 0x03
#define MCP3564_CONFIG2_AZ_REF_MASK BIT(1)
#define MCP3564_CONFIG2_AZ_MUX_MASK BIT(2)
#define MCP3564_CONFIG2_HARDWARE_GAIN_MASK GENMASK(5, 3)
#define MCP3564_DEFAULT_HARDWARE_GAIN 0x01
#define MCP3564_CONFIG2_BOOST_CURRENT_MASK GENMASK(7, 6)
#define MCP3564_CONFIG3_REG 0x04
#define MCP3464_CONFIG3_EN_GAINCAL_MASK BIT(0)
#define MCP3464_CONFIG3_EN_OFFCAL_MASK BIT(1)
#define MCP3464_CONFIG3_EN_CRCCOM_MASK BIT(2)
#define MCP3464_CONFIG3_CRC_FORMAT_MASK BIT(3)
/*
* ADC Output Data Format 32-bit (25-bit right justified data + Channel ID):
* CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data.
* It allows overrange with the SGN extension.
*/
#define MCP3464_CONFIG3_DATA_FMT_32B_WITH_CH_ID 3
/*
* ADC Output Data Format 32-bit (25-bit right justified data):
* SGN extension (8-bit) + 24-bit ADC data.
* It allows overrange with the SGN extension.
*/
#define MCP3464_CONFIG3_DATA_FMT_
