// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx AMS driver
*
* Copyright (C) 2021 Xilinx, Inc.
*
* Manish Narani <mnarani@xilinx.com>
* Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
*/
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devm-helpers.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/overflow.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
/* AMS registers definitions */
#define AMS_ISR_0 0x010
#define AMS_ISR_1 0x014
#define AMS_IER_0 0x020
#define AMS_IER_1 0x024
#define AMS_IDR_0 0x028
#define AMS_IDR_1 0x02C
#define AMS_PS_CSTS 0x040
#define AMS_PL_CSTS 0x044
#define AMS_VCC_PSPLL0 0x060
#define AMS_VCC_PSPLL3 0x06C
#define AMS_VCCINT 0x078
#define AMS_VCCBRAM 0x07C
#define AMS_VCCAUX 0x080
#define AMS_PSDDRPLL 0x084
#define AMS_PSINTFPDDR 0x09C
#define AMS_VCC_PSPLL0_CH 48
#define AMS_VCC_PSPLL3_CH 51
#define AMS_VCCINT_CH 54
#define AMS_VCCBRAM_CH 55
#define AMS_VCCAUX_CH 56
#define AMS_PSDDRPLL_CH 57
#define AMS_PSINTFPDDR_CH 63
#define AMS_REG_CONFIG0 0x100
#define AMS_REG_CONFIG1 0x104
#define AMS_REG_CONFIG3 0x10C
#define AMS_REG_CONFIG4 0x110
#define AMS_REG_SEQ_CH0 0x120
#define AMS_REG_SEQ_CH1 0x124
#define AMS_REG_SEQ_CH2 0x118
#define AMS_VUSER0_MASK BIT(0)
#define AMS_VUSER1_MASK BIT(1)
#define AMS_VUSER2_MASK BIT(2)
#define AMS_VUSER3_MASK BIT(3)
#define AMS_TEMP 0x000
#define AMS_SUPPLY1 0x004
#define AMS_SUPPLY2 0x008
#define AMS_VP_VN 0x00C
#define AMS_VREFP 0x010
#define AMS_VREFN 0x014
#define AMS_SUPPLY3 0x018
#define AMS_SUPPLY4 0x034
#define AMS_SUPPLY5 0x038
#define AMS_SUPPLY6 0x03C
#define AMS_SUPPLY7 0x200
#define AMS_SUPPLY8 0x204
#define AMS_SUPPLY9 0x208
#define AMS_SUPPLY10 0x20C
#define AMS_VCCAMS 0x210
#define AMS_TEMP_REMOTE 0x214
#define AMS_REG_VAUX(x) (0x40 + 4 * (x))
#define AMS_PS_RESET_VALUE 0xFFFF
#define AMS_PL_RESET_VALUE 0xFFFF
#define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0)
#define AMS_CONF1_SEQ_MASK GENMASK(15, 12)
#define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
#define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
#define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
#define AMS_REG_SEQ0_MASK GENMASK(15, 0)
#define AMS_REG_SEQ2_MASK GENMASK(21, 16)
#define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22)
#define AMS_PS_SEQ_MASK GENMASK(21, 0)
#define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22)
#define AMS_ALARM_TEMP 0x140
#define AMS_ALARM_SUPPLY1 0x144
#define AMS_ALARM_SUPPLY2 0x148
#define AMS_ALARM_SUPPLY3 0x160
#define AMS_ALARM_SUPPLY4 0x164
#define AMS_ALARM_SUPPLY5 0x168
#define AMS_ALARM_SUPPLY6 0x16C
#define AMS_ALARM_SUPPLY7 0x180
#define AMS_ALARM_SUPPLY8 0x184
#define AMS_ALARM_SUPPLY9 0x188
#define AMS_ALARM_SUPPLY10 0x18C
#define AMS_ALARM_VCCAMS 0x190
#define AMS_ALARM_TEMP_REMOTE 0x194
#define AMS_ALARM_THRESHOLD_OFF_10
