path: root/drivers/interconnect/qcom/qcs404.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Linaro Ltd
 */

#include <dt-bindings/interconnect/qcom,qcs404.h>
#include <linux/device.h>
#include <linux/interconnect-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>


#include "icc-rpm.h"

enum {
	QCS404_MASTER_AMPSS_M0 = 1,
	QCS404_MASTER_GRAPHICS_3D,
	QCS404_MASTER_MDP_PORT0,
	QCS404_SNOC_BIMC_1_MAS,
	QCS404_MASTER_TCU_0,
	QCS404_MASTER_SPDM,
	QCS404_MASTER_BLSP_1,
	QCS404_MASTER_BLSP_2,
	QCS404_MASTER_XM_USB_HS1,
	QCS404_MASTER_CRYPTO_CORE0,
	QCS404_MASTER_SDCC_1,
	QCS404_MASTER_SDCC_2,
	QCS404_SNOC_PNOC_MAS,
	QCS404_MASTER_QPIC,
	QCS404_MASTER_QDSS_BAM,
	QCS404_BIMC_SNOC_MAS,
	QCS404_PNOC_SNOC_MAS,
	QCS404_MASTER_QDSS_ETR,
	QCS404_MASTER_EMAC,
	QCS404_MASTER_PCIE,
	QCS404_MASTER_USB3,
	QCS404_PNOC_INT_0,
	QCS404_PNOC_INT_2,
	QCS404_PNOC_INT_3,
	QCS404_PNOC_SLV_0,
	QCS404_PNOC_SLV_1,
	QCS404_PNOC_SLV_2,
	QCS404_PNOC_SLV_3,
	QCS404_PNOC_SLV_4,
	QCS404_PNOC_SLV_6,
	QCS404_PNOC_SLV_7,
	QCS404_PNOC_SLV_8,
	QCS404_PNOC_SLV_9,
	QCS404_PNOC_SLV_10,
	QCS404_PNOC_SLV_11,
	QCS404_SNOC_QDSS_INT,
	QCS404_SNOC_INT_0,
	QCS404_SNOC_INT_1,
	QCS404_SNOC_INT_2,
	QCS404_SLAVE_EBI_CH0,
	QCS404_BIMC_SNOC_SLV,
	QCS404_SLAVE_SPDM_WRAPPER,
	QCS404_SLAVE_PDM,
	QCS404_SLAVE_PRNG,
	QCS404_SLAVE_TCSR,
	QCS404_SLAVE_SNOC_CFG,
	QCS404_SLAVE_MESSAGE_RAM,
	QCS404_SLAVE_DISPLAY_CFG,
	QCS404_SLAVE_GRAPHICS_3D_CFG,
	QCS404_SLAVE_BLSP_1,
	QCS404_SLAVE_TLMM_NORTH,
	QCS404_SLAVE_PCIE_1,
	QCS404_SLAVE_EMAC_CFG,
	QCS404_SLAVE_BLSP_2,
	QCS404_SLAVE_TLMM_EAST,
	QCS404_SLAVE_TCU,
	QCS404_SLAVE_PMIC_ARB,
	QCS404_SLAVE_SDCC_1,
	QCS404_SLAVE_SDCC_2,
	QCS404_SLAVE_TLMM_SOUTH,
	QCS404_SLAVE_USB_HS,
	QCS404_SLAVE_USB3,
	QCS404_SLAVE_CRYPTO_0_CFG,
	QCS404_PNOC_SNOC_SLV,
	QCS404_SLAVE_APPSS,
	QCS404_SLAVE_WCSS,
	QCS404_SNOC_BIMC_1_SLV,
	QCS404_SLAVE_OCIMEM,
	QCS404_SNOC_PNOC_SLV,
	QCS404_SLAVE_QDSS_STM,
	QCS404_SLAVE_CATS_128,
	QCS404_SLAVE_OCMEM_64,
	QCS404_SLAVE_LPASS,
};

static const u16 mas_apps_proc_links[] = {
	QCS404_SLAVE_EBI_CH0,
	QCS404_BIMC_SNOC_SLV
};

static struct qcom_icc_node mas_apps_proc = {
	.name = "mas_apps_proc",
	.id = QCS404_MASTER_AMPSS_M0,
	.buswidth = 8,
	.mas_rpm_id = 0,
	.slv_rpm_id = -1,
	.qos.ap_owned = true,
	.qos.qos_mode = NOC_QOS_MODE_FIXED,
	.qos.areq_prio = 0,
	.qos.prio_level = 0,
	.qos.qos_port = 0,
	.num_links = ARRAY_SIZE(mas_apps_proc_links),
	.links = mas_apps_proc_links,
};

static const u16 mas_oxili_links[] = {
	QCS404_SLAVE_EBI_CH0,
	QCS404_BIMC_SNOC_SLV
};

static struct qcom_icc_node mas_oxili = {
	.name = "mas_oxili",
	.id = QCS404_MASTER_GRAPHICS_3D,
	.buswidth = 8,
	.mas_rpm_id = -1,
	.slv_rpm_id = -1,
	.qos.ap_owned = true,
	.qos.qos_mode = NOC_QOS_MODE_FIXED,
	.qos.areq_prio = 0,
	.qos.prio_level = 0,
	.qos.qos_port = 2,
	.num_links = ARRAY_SIZE(mas_oxili_links),
	.links = mas_oxili_links,
};

static const u16 mas_mdp_links[] = {
	QCS404_SLAVE_EBI_CH0,
	QCS404_BIMC_SNOC_SLV
};

static struct qcom_icc_node mas_mdp = {
	.name = "mas_mdp",
	.id = QCS404_MASTER_MDP_PORT0,
	.buswidth = 8,
	.mas_rpm_id = -1,
	.slv_rpm_id = -1,
	.qos.ap_owned = true,
	.qos.qos_mode = NOC_QOS_MODE_FIXED,
	.qos.areq_prio = 0,
	.qos.prio_level = 1,
	.qos.qos_port = 4,
	.num_links = ARRAY_SIZE(mas_mdp_links),
	.links = mas_mdp_links,
};

static const u16 mas_snoc_bimc_1_links[] = {
	QCS404_SLAVE_EBI_CH0
};

static struct qcom_icc_node mas_snoc_bimc_1 = {
	.name = "mas_snoc_bimc_1",
	.id = QCS404_SNOC_BIMC_1_MAS,
	.buswidth = 8,
	.mas_rpm_id = 76,
	.</