// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
#include "qdu1000.h"
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = QDU1000_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_QUP_CORE_0 },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
.id = QDU1000_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_QUP_CORE_1 },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = QDU1000_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
.id = QDU1000_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 4,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qnm_ecpri_dma = {
.name = "qnm_ecpri_dma",
.id = QDU1000_MASTER_GEMNOC_ECPRI_DMA,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_fec_2_gemnoc = {
.name = "qnm_fec_2_gemnoc",
.id = QDU1000_MASTER_FEC_2_GEMNOC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 64,
.num_links = 3,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC
},
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = QDU1000_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QDU1000_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = QDU1000_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 4,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qxm_mdsp = {
.name = "qxm_mdsp",
.id = QDU1000_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = QDU1000_MASTER_LLCC,
.channels = 8,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_EBI1 },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.id = QDU1000_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = QDU1000_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = QDU1000_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
.id = QDU1000_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.id = QDU1000_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { QDU1000_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.id = QDU1000_MASTER_QUP_1,
.channels = 1,
.buswidth = 4