path: root/drivers/mailbox/imx-mailbox.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
 */

#include <linux/clk.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/s4.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
#include <linux/slab.h>

#define IMX_MU_CHANS		16
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS	6
/* TX0/RX0 */
#define IMX_MU_S4_CHANS		2
#define IMX_MU_CHAN_NAME_SIZE	20

#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))

/* Please not change TX & RX */
enum imx_mu_chan_type {
	IMX_MU_TYPE_TX		= 0, /* Tx */
	IMX_MU_TYPE_RX		= 1, /* Rx */
	IMX_MU_TYPE_TXDB	= 2, /* Tx doorbell */
	IMX_MU_TYPE_RXDB	= 3, /* Rx doorbell */
};

enum imx_mu_xcr {
	IMX_MU_GIER,
	IMX_MU_GCR,
	IMX_MU_TCR,
	IMX_MU_RCR,
	IMX_MU_xCR_MAX,
};

enum imx_mu_xsr {
	IMX_MU_SR,
	IMX_MU_GSR,
	IMX_MU_TSR,
	IMX_MU_RSR,
};

struct imx_sc_rpc_msg_max {
	struct imx_sc_rpc_msg hdr;
	u32 data[30];
};

struct imx_s4_rpc_msg_max {
	struct imx_s4_rpc_msg hdr;
	u32 data[254];
};

struct imx_mu_con_priv {
	unsigned int		idx;
	char			irq_desc[IMX_MU_CHAN_NAME_SIZE];
	enum imx_mu_chan_type	type;
	struct mbox_chan	*chan;
	struct tasklet_struct	txdb_tasklet;
};

struct imx_mu_priv {
	struct device		*dev;
	void __iomem		*base;
	void			*msg;
	spinlock_t		xcr_lock; /* control register lock */

	struct mbox_controller	mbox;
	struct mbox_chan	mbox_chans[IMX_MU_CHANS];

	struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
	const struct imx_mu_dcfg	*dcfg;
	struct clk		*clk;
	int			irq[IMX_MU_CHANS];
	bool			suspend;

	u32 xcr[4];

	bool			side_b;
};

enum imx_mu_type {
	IMX_MU_V1,
	IMX_MU_V2 = BIT(1),
	IMX_MU_V2_S4 = BIT(15),
	IMX_MU_V2_IRQ = BIT(16),
};

struct imx_mu_dcfg {
	int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
	int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
	int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
	void (*init)(struct imx_mu_priv *priv);
	enum imx_mu_type type;
	u32	xTR;		/* Transmit Register0 */
	u32	xRR;		/* Receive Register0 */
	u32	xSR[4];		/* Status Registers */
	u32	xCR[4];		/* Control Registers */
};

#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))

/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))


static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
	return container_of(mbox, struct imx_mu_priv, mbox);
}

static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
{
	iowrite32(val, priv->base + offs);
}

static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
{
	return ioread32(priv->base + offs);
}

static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
{
	u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
	u32 status;
	u32 can_write;

	dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);

	do {
		status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
		can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
	} while (!can_write && time_is_after_jiffies64(timeout_time));

	if (!can_write) {
		dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
			val, idx, status);
		return -ETIME;
	}

	imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);

	return 0;
}

static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
{
	u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
	u32 status;
	u32 can_read;

	dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);

	do {
		status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
		can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
	} while (!can_read && time_is_after_jiffies64(timeout_time));

	if (!can_read) {
		dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
			idx, status);
		return -ETIME;
	}

	*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
	dev_dbg(priv->dev, "Read %.8x\n", *val);

	return 0;
}

static u32 imx_mu_xcr_rmw(struct imx_mu_priv <