path: root/drivers/media/i2c/ov13b10.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Intel Corporation.

#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>

#define OV13B10_REG_VALUE_08BIT		1
#define OV13B10_REG_VALUE_16BIT		2
#define OV13B10_REG_VALUE_24BIT		3

#define OV13B10_REG_MODE_SELECT		0x0100
#define OV13B10_MODE_STANDBY		0x00
#define OV13B10_MODE_STREAMING		0x01

#define OV13B10_REG_SOFTWARE_RST	0x0103
#define OV13B10_SOFTWARE_RST		0x01

/* Chip ID */
#define OV13B10_REG_CHIP_ID		0x300a
#define OV13B10_CHIP_ID			0x560d42

/* V_TIMING internal */
#define OV13B10_REG_VTS			0x380e
#define OV13B10_VTS_30FPS		0x0c7c
#define OV13B10_VTS_60FPS		0x063e
#define OV13B10_VTS_MAX			0x7fff

/* HBLANK control - read only */
#define OV13B10_PPL_560MHZ		4704

/* Exposure control */
#define OV13B10_REG_EXPOSURE		0x3500
#define OV13B10_EXPOSURE_MIN		4
#define OV13B10_EXPOSURE_STEP		1
#define OV13B10_EXPOSURE_DEFAULT	0x40

/* Analog gain control */
#define OV13B10_REG_ANALOG_GAIN		0x3508
#define OV13B10_ANA_GAIN_MIN		0x80
#define OV13B10_ANA_GAIN_MAX		0x07c0
#define OV13B10_ANA_GAIN_STEP		1
#define OV13B10_ANA_GAIN_DEFAULT	0x80

/* Digital gain control */
#define OV13B10_REG_DGTL_GAIN_H		0x350a
#define OV13B10_REG_DGTL_GAIN_M		0x350b
#define OV13B10_REG_DGTL_GAIN_L		0x350c

#define OV13B10_DGTL_GAIN_MIN		1024	     /* Min = 1 X */
#define OV13B10_DGTL_GAIN_MAX		(4096 - 1)   /* Max = 4 X */
#define OV13B10_DGTL_GAIN_DEFAULT	2560	     /* Default gain = 2.5 X */
#define OV13B10_DGTL_GAIN_STEP		1	     /* Each step = 1/1024 */

#define OV13B10_DGTL_GAIN_L_SHIFT	6
#define OV13B10_DGTL_GAIN_L_MASK	0x3
#define OV13B10_DGTL_GAIN_M_SHIFT	2
#define OV13B10_DGTL_GAIN_M_MASK	0xff
#define OV13B10_DGTL_GAIN_H_SHIFT	10
#define OV13B10_DGTL_GAIN_H_MASK	0x3

/* Test Pattern Control */
#define OV13B10_REG_TEST_PATTERN	0x5080
#define OV13B10_TEST_PATTERN_ENABLE	BIT(7)
#define OV13B10_TEST_PATTERN_MASK	0xf3
#define OV13B10_TEST_PATTERN_BAR_SHIFT	2

/* Flip Control */
#define OV13B10_REG_FORMAT1		0x3820
#define OV13B10_REG_FORMAT2		0x3821

/* Horizontal Window Offset */
#define OV13B10_REG_H_WIN_OFFSET	0x3811

/* Vertical Window Offset */
#define OV13B10_REG_V_WIN_OFFSET	0x3813

struct ov13b10_reg {
	u16 address;
	u8 val;
};

struct ov13b10_reg_list {
	u32 num_of_regs;
	const struct ov13b10_reg *regs;
};

/* Link frequency config */
struct ov13b10_link_freq_config {
	u32 pixels_per_line;

	/* registers for this link frequency */
	struct ov13b10_reg_list reg_list;
};

/* Mode : resolution and related config&values */
struct ov13b10_mode {
	/* Frame width */
	u32 width;
	/* Frame height */
	u32 height;

	/* V-timing */
	u32 vts_def;
	u32 vts_min;

	/* Index of Link frequency config to be used */
	u32 link_freq_index;
	/* Default register values */
	struct ov13b10_reg_list reg_list;
};

/* 4208x3120 needs 1120Mbps/lane, 4 lanes */
static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
	{0x0103, 0x01},
	{0x0303, 0x04},
	{0x0305, 0xaf},
	{0x0321, 0x00},
	{0x0323, 0x04},
	{0x0324, 0x01},
	{0x0325, 0xa4},
	{0x0326, 0x81},
	{0x0327, 0x04},
	{0x3012, 0x07},
	{0x3013, 0x32},
	{0x3107, 0x23},
	{0x3501, 0x0c},
	{0x3502, 0x10},
	{0x3504, 0x08},
	{0x3508, 0x07},
	{0x3509, 0xc0},
	{0x3600, 0x16},
	{0x3601, 0x54},
	{0x3612, 0x4e},
	{0x3620, 0x00},
	{0x3621, 0x68},
	{0x3622, 0x66},
	{0x3623, 0x03},
	{0x3662, 0x92},
	{0x3666, 0xbb},
	{0x3667, 0x44},
	{0x366e, 0xff},
	{0x366f, 0xf3},
	{0x3675, 0x44},
	{0x3676, 0x00},
	{0x367f, 0xe9},
	{0x3681, 0x32},
	{0x3682, 0x1f},
	{0x3683, 0x0b},
	{0x3684, 0x0b},
	{0x3704, 0x0f},
	{0x3706, 0x40},
	{0x3708, 0x3b},
	{0x3709, 0x72},
	{0x370b, 0xa2},
	{0x3714, 0x24},
	{0x371a, 0x3e},
	{0x3725, 0x42},
	{0x3739, 0x12},
	{0x3767, 0x00},
	{0x377a, 0x0d},
	{0x3789, 0x18},
	{0x3790, 0x40},
	{0x3791, 0xa2},
	{0x37c2, 0x04},
	{0x37c3, 0xf1},
	{0x37d9, 0x0c},
	{0x37da, 0x02},
	{0x37dc, 0x02},
	{0x37e1, 0x04},
	{0x37e2, 0x0a},
	{0x3800, 0x00},
	{0x3801, 0x00},
	{0x3802, 0x00},
	{0x3803, 0x08},
	{0x3804, 0x10},
	{0x3805, 0x8f},
	{0x3806, 0x0c},
	{0x3807, 0x47},
	{0x3808, 0x10},
	{0x3809, 0x70},
	{0x380a, 0x0c},
	{0x380b, 0x30},
	{0x380c, 0x04},
	{0x380d, 0x98},
	{0x380e, 0x0c},
	{0x380f, 0x7c},
	{0x3811, 0x0f},
	{0x3813, 0x09},
	{0x3814, 0x01},
	{0x3815, 0x01},
	{0x3816, 0x01},
	{0x3817, 0x01},
	{0x381f, 0x08},
	{0x3820, 0x88},
	{0x3821, 0x00},
	{0x3822, 0x14},
	{0x382e, 0xe6},
	{0x3c80, 0x00},
	{0x3c87, 0x01},
	{0x3c8c, 0x19},
	{0x3c8d, 0x1c},
	{0x3ca0, 0x00},
	{0x3ca1, 0x00},
	{0x3ca2, 0x00},
	{0x3ca3, 0x00},
	{0x3ca4, 0x50},
	{0x3ca5, 0x11},
	{0x3ca6, 0x01},
	{0x3ca7, 0x00},
	{0x3ca8, 0x00},
	{0x4008, 0x02},
	{0x4009, 0x0f},
	{0x400a, 0x01},
	{0x400b, 0x19},
	{0x4011, 0x21},
	{0x4017, 0x08},
	{0x4019, 0x04},
	{0x401a, 0x58},
	{0x4032, 0x1e},
	{0x4050, 0x02},
	{0x4051, 0x09},
	{0x405e, 0x00},
	{0x4066, 0x02},
	{0x4501, 0x00},
	{0x4502, 0x10},
	{0x4505, 0x00},
	{0x4800, 0x64},
	{0x481b, 0x3e},
	{0x481f, 0x30},
	{0x4825, 0x34},
	{0x4837, 0x0e},
	{0x484b, 0x01},
	{0x4883, 0x02},
	{0x5000, 0xff},
	{0x5001, 0x0f},
	{0x5045, 0x20},
	{0x5046, 0x20},
	{0x5047, 0xa4},
	{0x5048, 0x20},
	{0x5049, 0xa4},
	{0x0100, 0x01},
};

static const struct ov13b10_reg mode_4208x3120_regs[] = {
	{0x0305, 0xaf},
	{0x3501, 0x0c},
	{0x3662, 0x92},
	{0x3714, 0x24},
	{0x3739, 0x12},
	{0x37c2, 0x04},
	{0x37d9, 0x0c},
	{0x37e2, 0x0a},
	{0x3800, 0x00},
	{0x3801, 0x00},
	{0x3802, 0x00},
	{0x3803, 0x08},
	{0x3804, 0x10},
	{0x3805, 0x8f},
	{0x3806, 0x0c},
	{0x3807, 0x47},
	{0x3808, 0x10},
	{0x3809, 0x70},
	{0x380a, 0x0c},
	{0x380b, 0x30},
	{0x380c, 0x04},
	{0x380d, 0x98},
	{0x380e, 0x0c},
	{0x380f, 0x7c},
	{0x3810, 0x00},
	{0x3811, 0x0f},
	{0x3812, 0x00},
	{0x3813, 0x09},
	{0x3814, 0x01},
	{0x3816, 0x01},
	{0x3820, 0x88},
	{0x3c8c, 0x19},
	{0x4008, 0x02},
	{0x4009, 0x0f},
	{0x4050, 0x02},
	{0x4051, 0x09},
	{0x4501, 0x00},
	{0x4505, 0x00},
	{0x4837, 0x0e},
	{0x5000, 0xff},
	{0x5001, 0x0f},
};

static const struct ov13b10_reg mode_4160x3120_regs[] = {
	{0x0305, 0xaf},
	{0x3501, 0x0c},
	{0x3662, 0x92},
	{0x3714, 0x24},
	{0x3739, 0x12},
	{0x37c2, 0x04},
	{0x37d9, 0x0c},
	{0x37e2, 0x0a},
	{0x3800, 0x00},
	{0x3801, 0x00},
	{0x3802, 0x00},
	{0x3803, 0x08},
	{0x3804, 0x10},
	{0x3805, 0x8f},
	{0x3806, 0x0c},
	{0x3807, 0x47},
	{0x3808, 0x10},
	{0x3809, 0x40},
	{0x380a, 0x0c},
	{0x380b, 0x30},
	{0x380c, 0x04},
	{0x380d, 0x98},
	{0x380e, 0x0c},
	{0x380f, 0x7c},
	{0x3810, 0x00},
	{0x3811, 0x27},
	{0x3812, 0x00},
	{0x3813, 0x09},
	{0x3814, 0x01},
	{0x3816, 0x01},
	{0x3820, 0x88},
	{0x3c8c, 0x19},
	{0x4008, 0x02},
	{0x4009, 0x0f},
	{0x4050, 0x02},
	{0x4051, 0x09},
	{0x4501, 0x00},
	{0x4505, 0x00},
	{0x4837, 0x0e},
	{0x5000, 0xff},
	{0x5001, 0x0f},
};

static const struct ov13b10_reg mode_4160x2340_regs[] = {
	{0x0305, 0xaf},
	{0x3501, 0x0c},
	{0x3662, 0x92},
	{0x3714, 0x24},
	{0x3739, 0x12},
	{0x37c2, 0x04},
	{0x37d9, 0x0c},
	{0x37e2, 0x0a},
	{0x3800, 0x00},
	{0x3801, 0x00},
	{0x3802, 0x00},
	{0x3803, 0x08},
	{0x3804, 0x10},
	{0x3805, 0x8f},
	{0x3806, 0x0c},
	{0x3807, 0x47},
	{0x3808, 0x10},
	{0x3809, 0x40},
	{0x380a, 0x09},
	{0x380b, 0x24},
	{0x380c, 0x04},
	{0x380d, 0x98},
	{0x380e, 0x0c},
	{0x380f, 0x7c},
	{0x3810, 0x00},
	{0x3811, 0x27},
	{0x3812, 0x01},
	{0x3813, 0x8f},
	{0x3814, 0x01},
	{0x3816, 0x01},
	{0x3820, 0x88},
	{0x3c8c, 0x19},
	{0x4008, 0x02},
	{0x4009, 0x0f},
	{0x4050, 0x02},
	{0x4051, 0x09},
	{0x4501, 0x00},
	{0x4505, 0x00},
	{0x4837, 0x0e},
	{0x5000, 0xff},
	{0x5001, 0x0f},
};

static const struct ov13b10_reg mode_2104x1560_regs[] = {
	{0x0305, 0xaf},
	{0x3501, 0x06},
	{0x3662, 0x88},
	{0x3714, 0x28},
	{0x3739, 0x10},
	{0x37c2, 0x14},
	{0x37d9, 0x06},
	{0x37e2, 0x0c},
	{0x3800, 0x00},
	{0x3801, 0x00},
	{0x3802, 0x00},
	{0x3803, 0x08},
	{0x3804, 0x10},
	{0x3805, 0x8f},
	{0x3806, 0x0c},
	{0x3807, 0x47},
	{0x3808, 0x08},
	{0x3809, 0x38},
	{0x380a, 0x06},
	{0x380b, 0x18},
	{0x380c, 0x04},
	{0x380d, 0x98},
	{0x380e, 0x06},
	{0x380f, 0x3e},
	{0x3810, 0x00},
	{0x3811, 0x07},
	{0x3812, 0x00},
	{0x3813, 0x05},
	{0x3814, 0x03},
	{0x3816, 0x03},
	{0x3820, 0x8b},