path: root/drivers/media/i2c/ov4689.c

// SPDX-License-Identifier: GPL-2.0
/*
 * ov4689 driver
 *
 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
 * Copyright (C) 2022 Mikhail Rudenko
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <media/media-entity.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-fwnode.h>

#define CHIP_ID				0x004688
#define OV4689_REG_CHIP_ID		0x300a

#define OV4689_XVCLK_FREQ		24000000

#define OV4689_REG_CTRL_MODE		0x0100
#define OV4689_MODE_SW_STANDBY		0x0
#define OV4689_MODE_STREAMING		BIT(0)

#define OV4689_REG_EXPOSURE		0x3500
#define OV4689_EXPOSURE_MIN		4
#define OV4689_EXPOSURE_STEP		1
#define OV4689_VTS_MAX			0x7fff

#define OV4689_REG_GAIN_H		0x3508
#define OV4689_REG_GAIN_L		0x3509
#define OV4689_GAIN_H_MASK		0x07
#define OV4689_GAIN_H_SHIFT		8
#define OV4689_GAIN_L_MASK		0xff
#define OV4689_GAIN_STEP		1
#define OV4689_GAIN_DEFAULT		0x80

#define OV4689_REG_TEST_PATTERN		0x5040
#define OV4689_TEST_PATTERN_ENABLE	0x80
#define OV4689_TEST_PATTERN_DISABLE	0x0

#define OV4689_REG_VTS			0x380e

#define REG_NULL			0xFFFF

#define OV4689_REG_VALUE_08BIT		1
#define OV4689_REG_VALUE_16BIT		2
#define OV4689_REG_VALUE_24BIT		3

#define OV4689_LANES			4

static const char *const ov4689_supply_names[] = {
	"avdd", /* Analog power */
	"dovdd", /* Digital I/O power */
	"dvdd", /* Digital core power */
};

struct regval {
	u16 addr;
	u8 val;
};

enum ov4689_mode_id {
	OV4689_MODE_2688_1520 = 0,
	OV4689_NUM_MODES,
};

struct ov4689_mode {
	enum ov4689_mode_id id;
	u32 width;
	u32 height;
	u32 max_fps;
	u32 hts_def;
	u32 vts_def;
	u32 exp_def;
	u32 pixel_rate;
	u32 sensor_width;
	u32 sensor_height;
	u32 crop_top;
	u32 crop_left;
	const struct regval *reg_list;
};

struct ov4689 {
	struct i2c_client *client;
	struct clk *xvclk;
	struct gpio_desc *reset_gpio;
	struct gpio_desc *pwdn_gpio;
	struct regulator_bulk_data supplies[ARRAY_SIZE(ov4689_supply_names)];

	struct v4l2_subdev subdev;
	struct media_pad pad;

	u32 clock_rate;

	struct mutex mutex; /* lock to protect ctrls and cur_mode */
	struct v4l2_ctrl_handler ctrl_handler;
	struct v4l2_ctrl *exposure;

	const struct ov4689_mode *cur_mode;
};

#define to_ov4689(sd) container_of(sd, struct ov4689, subdev)

struct ov4689_gain_range {
	u32 logical_min;
	u32 logical_max;
	u32 offset;
	u32 divider;
	u32 physical_min;
	u32 physical_max;
};

/*
 * Xclk 24Mhz
 * max_framerate 30fps
 * mipi_datarate per lane 1008Mbps
 */
static const struct regval ov4689_2688x1520_regs[] = {
	{0x0103, 0x01}, {0x3638, 0x00}, {0x0300, 0x00},
	{0x0302, 0x2a}, {0x0303, 0x00}, {0x0304, 0x03},
	{0x030b, 0x00}, {0x030d, 0x1e}, {0x030e, 0x04},
	{0x030f, 0x01}, {0x0312, 0x01}, {0x031e, 0x00},
	{0x3000, 0x20}, {0x3002, 0x00}, {0x3018, 0x72},
	{0x3020, 0x93}, {0x3021, 0x03}, {0x3022, 0x01},
	{0x3031, 0x0a}, {0x303f, 0x0c}, {0x3305, 0xf1},
	{0x3307, 0x04}, {0x3309, 0x29}, {0x3500, 0x00},
	{0x3501, 0x60}, {0x3502, 0x00}, {0x3503, 0x04},
	{0x3504, 0x00}, {0x3505, 0x00}, {0x3506, 0x00},
	{0x3507, 0x00}, {0x3508, 0x00}, {0x3509, 0x80},
	{0x350a, 0x00}, {0x350b, 0x00}, {0x350c, 0x00},
	{0x350d, 0x00}, {0x350e, 0x00}, {0x350f, 0x80},
	{0x3510, 0x00}, {0x3511, 0x00}, {0x3512, 0x00},
	{0x3513, 0x00}, {0x3514, 0x00}, {0x3515, 0x80},
	{0x3516, 0x00}, {0x3517, 0x00}, {0x3518, 0x00},
	{0x3519, 0x00}, {0x351a, 0x00}, {0x351b, 0x80},
	{0x351c, 0x00}, {0x351d, 0x00}, {0x351e, 0x00},
	{0x351f, 0x00}, {0x3520, 0x00}, {0x3521, 0x80},
	{0x3522, 0x08}, {0x3524, 0x08}, {0x3526, 0x08},
	{0x3528, 0x08}, {0x352a, 0x08}, {0x3602, 0x00},
	{0x3603, 0x40}, {0x3604, 0x02}, {0x3605, 0x00},
	{0x3606, 0x00}, {0x3607, 0x00}, {0x3609, 0x12},
	{0x360a, 0x40}, {0x360c, 0x08}, {0x360f, 0xe5},
	{0x3608, 0x8f}, {0x3611, 0x00}, {0x3613, 0xf7},
	{0x3616, 0x58}, {0x3619, 0x99}, {0x361b, 0x60},
	{0x361c, 0x7a}, {0x361e, 0x79}, {0x361f, 0x02},
	{0x3632, 0x00}, {0x3633, 0x10}, {0x3634, 0x10},
	{0x3635, 0x10}, {0x3636, 0x15}, {0x3646, 0x86},
	{0x364a, 0x0b}, {0x3700, 0x17}, {0x3701, 0x22},
	{0x3703, 0x10}, {0x370a, 0x37}, {0x3705, 0x00},
	{0x3706, 0x63}, {0x3709, 0x3c}, {0x370b, 0x01},
	{0x370c, 0x30}, {0x3710, 0x24}, {0x3711, 0x0c},
	{0x3716, 0x00}, {0x3720, 0x28}, {0x3729, 0x7b},