path: root/drivers/media/i2c/ov7251.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for the OV7251 camera sensor.
 *
 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2017-2018, Linaro Ltd.
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>

#define OV7251_SC_MODE_SELECT		0x0100
#define OV7251_SC_MODE_SELECT_SW_STANDBY	0x0
#define OV7251_SC_MODE_SELECT_STREAMING		0x1

#define OV7251_CHIP_ID_HIGH		0x300a
#define OV7251_CHIP_ID_HIGH_BYTE	0x77
#define OV7251_CHIP_ID_LOW		0x300b
#define OV7251_CHIP_ID_LOW_BYTE		0x50
#define OV7251_SC_GP_IO_IN1		0x3029
#define OV7251_AEC_EXPO_0		0x3500
#define OV7251_AEC_EXPO_1		0x3501
#define OV7251_AEC_EXPO_2		0x3502
#define OV7251_AEC_AGC_ADJ_0		0x350a
#define OV7251_AEC_AGC_ADJ_1		0x350b
#define OV7251_TIMING_FORMAT1		0x3820
#define OV7251_TIMING_FORMAT1_VFLIP	BIT(2)
#define OV7251_TIMING_FORMAT2		0x3821
#define OV7251_TIMING_FORMAT2_MIRROR	BIT(2)
#define OV7251_PRE_ISP_00		0x5e00
#define OV7251_PRE_ISP_00_TEST_PATTERN	BIT(7)

struct reg_value {
	u16 reg;
	u8 val;
};

struct ov7251_mode_info {
	u32 width;
	u32 height;
	const struct reg_value *data;
	u32 data_size;
	u32 pixel_clock;
	u32 link_freq;
	u16 exposure_max;
	u16 exposure_def;
	struct v4l2_fract timeperframe;
};

struct ov7251 {
	struct i2c_client *i2c_client;
	struct device *dev;
	struct v4l2_subdev sd;
	struct media_pad pad;
	struct v4l2_fwnode_endpoint ep;
	struct v4l2_mbus_framefmt fmt;
	struct v4l2_rect crop;
	struct clk *xclk;
	u32 xclk_freq;

	struct regulator *io_regulator;
	struct regulator *core_regulator;
	struct regulator *analog_regulator;

	const struct ov7251_mode_info *current_mode;

	struct v4l2_ctrl_handler ctrls;
	struct v4l2_ctrl *pixel_clock;
	struct v4l2_ctrl *link_freq;
	struct v4l2_ctrl *exposure;
	struct v4l2_ctrl *gain;

	/* Cached register values */
	u8 aec_pk_manual;
	u8 pre_isp_00;
	u8 timing_format1;
	u8 timing_format2;

	struct mutex lock; /* lock to protect power state, ctrls and mode */
	bool power_on;

	struct gpio_desc *enable_gpio;
};

static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
{
	return container_of(sd, struct ov7251, sd);
}

static const struct reg_value ov7251_global_init_setting[] = {
	{ 0x0103, 0x01 },
	{ 0x303b, 0x02 },
};

static const struct reg_value ov7251_setting_vga_30fps[] = {
	{ 0x3005, 0x00 },
	{ 0x3012, 0xc0 },
	{ 0x3013, 0xd2 },
	{ 0x3014, 0x04 },
	{ 0x3016, 0xf0 },
	{ 0x3017, 0xf0 },
	{ 0x3018, 0xf0 },
	{ 0x301a, 0xf0 },
	{ 0x301b, 0xf0 },
	{ 0x301c, 0xf0 },
	{ 0x3023, 0x05 },
	{ 0x3037, 0xf0 },
	{ 0x3098, 0x04 }, /* pll2 pre divider */
	{ 0x3099, 0x28 }, /* pll2 multiplier */
	{ 0x309a, 0x05 }, /* pll2 sys divider */
	{ 0x309b, 0x04 }, /* pll2 adc divider */
	{ 0x309d, 0x00 }, /* pll2 divider */
	{ 0x30b0, 0x0a }, /* pll1 pix divider */
	{ 0x30b1, 0x01 }, /* pll1 divider */
	{ 0x30b3, 0x64 }, /* pll1 multiplier */
	{ 0x30b4, 0x03 }, /* pll1 pre divider */
	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
	{ 0x3106, 0xda },
	{ 0x3503, 0x07 },
	{ 0x3509, 0x10 },
	{ 0x3600, 0x1c },
	{ 0x3602, 0x62 },
	{ 0x3620, 0xb7 },
	{ 0x3622, 0x04 },
	{ 0x3626, 0x21 },
	{ 0x3627, 0x30 },
	{ 0x3630, 0x44 },
	{ 0x3631, 0x35 },
	{ 0x3634, 0x60 },
	{ 0x3636, 0x00 },
	{ 0x3662, 0x01 },
	{ 0x3663, 0x70 },
	{ 0x3664, 0x50 },
	{ 0x3666, 0x0a },
	{ 0x3669, 0x1a },
	{ 0x366a, 0x00 },
	{ 0x366b, 0x50 },
	{ 0x3673, 0x01 },
	{ 0x3674, 0xff },
	{ 0x3675, 0x03 },
	{ 0x3705, 0xc1 },
	{ 0x3709, 0x40 },
	{ 0x373c, 0x08 },
	{ 0x3742, 0x00 },
	{ 0x3757, 0xb3 },
	{ 0x3788, 0x00 },
	{ 0x37a8, 0x01 },
	{ 0x37a9, 0xc0 },
	{ 0x3800, 0x00 },
	{ 0x3801, 0x04 },
	{ 0x3802, 0x00 },
	{ 0x3803, 0x04 },
	{ 0x3804, 0x02 },
	{ 0x3805, 0x8b },
	{ 0x3806, 0x01 },
	{ 0x3807, 0xeb },
	{ 0x3808, 0x02 }, /* width high */
	{ 0x3809, 0x80 }, /* width low */
	{ 0x380a, 0x01 }, /* height high */
	{ 0x380b, 0xe0 }, /* height low */
	{ 0x380c, 0x03 }, /* total horiz timing high */
	{ 0x380d, 0xa0 }, /* total horiz timing low */
	{ 0x380e, 0x06 }, /* total vertical timing high */
	{ 0x380f, 0xbc }, /* total vertical timing low */
	{ 0x3810, 0x00 },
	{ 0x3811, 0x04 },
	{ 0x3812, 0x00 },
	{ 0x3813, 0x05 },
	{ 0x3814, 0x11 },
	{ 0x3815, 0x11 },
	{ 0x3820, 0x40 },
	{ 0x3821, 0x00 },
	{ 0x382f, 0x0e },
	{ 0x3832, 0x00 },
	{ 0x3833, 0x05 },
	{ 0x3834, 0x00 },
	{ 0x3835, 0x0c },
	{ 0x3837, 0x00 },
	{ 0x3b80, 0x00 },
	{ 0x3b81, 0xa5 },
	{ 0x3b82, 0x10 },
	{ 0x3b83, 0x00 },
	{ 0x3b84, 0x08 },
	{ 0x3b85, 0x00 },
	{ 0x3b86, 0x01 },
	{ 0x3b87, 0x00 },
	{ 0x3b88, 0x00 },
	{ 0x3b89, 0x00 },
	{ 0x3b8a, 0x00 },
	{ 0x3b8b, 0x05 },
	{ 0x3b8c, 0x00 },
	{ 0x3b8d, 0x00 },
	{ 0x3b8e, 0x00 },
	{ 0x3b8f, 0x1a },
	{ 0x3b94, 0x05 },
	{ 0x3b95, 0xf2 },
	{ 0x3b96, 0x40 },
	{ 0x3c00, 0x89 },
	{ 0x3c01, 0x63 },
	{ 0x3c02, 0x01 },
	{ 0x3c03, 0x00 },
	{ 0x3c04, 0x00 },
	{ 0x3c05, 0x03 },
	{ 0x3c06, 0x00 },
	{ 0x3c07, 0x06 },
	{ 0x3c0c, 0x01 },
	{ 0x3c0d, 0xd0 },
	{ 0x3c0e, 0x02 },
	{ 0x3c0f, 0x0a },
	{ 0x4001, 0x42 },
	{ 0x4004, 0x04 },
	{ 0x4005, 0x00 },
	{ 0x404e, 0x01 },
	{ 0x4300, 0xff },
	{ 0x4301, 0x00 },
	{ 0x4315, 0x00 },
	{ 0x4501, 0x48 },
	{ 0x4600, 0x00 },
	{ 0x4601, 0x4e },
	{ 0x4801, 0x0f },
	{ 0x4806, 0x0f },
	{ 0x4819, 0xaa },
	{ 0x4823, 0x3e },
	{ 0x4837, 0x19 },
	{ 0x4a0d, 0x00 },
	{ 0x4a47, 0x7f },
	{ 0x4a49, 0xf0 },
	{ 0x4a4b, 0x30 },
	{ 0x5000, 0x85 },
	{ 0x5001, 0x80 },
};

static const struct reg_value ov7251_setting_vga_60fps[] = {
	{ 0x3005, 0x00 },
	{ 0x3012, 0xc0 },
	{ 0x3013, 0xd2 },
	{ 0x3014, 0x04 },
	{ 0x3016, 0x10 },
	{ 0x3017, 0x00 },
	{ 0x3018, 0x00 },
	{ 0x301a, 0x00 },
	{ 0x301b, 0x00 },
	{ 0x301c, 0x00 },
	{ 0x3023, 0x05 },
	{ 0x3037, 0xf0 },
	{ 0x3098, 0x04 }, /* pll2 pre divider */
	{ 0x3099, 0x28 }, /* pll2 multiplier */
	{ 0x309a, 0x05 }, /* pll2 sys divider */
	{ 0x309b, 0x04 }, /* pll2 adc divider */
	{ 0x309d, 0x00 }, /* pll2 divider */
	{ 0x30b0, 0x0a }, /* pll1 pix divider */
	{ 0x30b1, 0x01 }, /* pll1 divider */
	{ 0x30b3, 0x64 }, /* pll1 multiplier */
	{ 0x30b4, 0x03 }, /* pll1 pre divider */
	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
	{ 0x3106, 0xda },
	{ 0x3503, 0x07 },
	{ 0x3509, 0x10 },
	{ 0x3600, 0x1c },
	{ 0x3602, 0x62 },
	{ 0x3620, 0xb7 },
	{ 0x3622, 0x04 },
	{ 0x3626, 0x21 },
	{ 0x3627, 0x30 },
	{ 0x3630, 0x44 },
	{ 0x3631, 0x35 },
	{ 0x3634, 0x60 },
	{ 0x3636, 0x00 },
	{ 0x3662, 0x01 },
	{ 0x3663, 0x70 },
	{ 0x3664, 0x50 },
	{ 0x3666, 0x0a },
	{ 0x3669, 0x1a },
	{ 0x366a, 0x00 },
	{ 0x366b, 0x50 },
	{ 0x3673, 0x01 },
	{ 0x3674, 0xff },
	{ 0x3675, 0x03 },
	{ 0x3705, 0xc1 },
	{ 0x3709, 0x40 },
	{ 0x373c, 0x08 },
	{ 0x3742, 0x00 },
	{ 0x3757, 0xb3 },
	{ 0x3788, 0x00 },
	{ 0x37a8, 0x01 },
	{ 0x37a9, 0xc0 },
	{ 0x3800, 0x00 },
	{ 0x3801, 0x04 },
	{ 0x3802, 0x00 },
	{ 0x3803, 0x04 },
	{ 0x3804, 0x02 },
	{ 0x3805, 0x8b },
	{ 0x3806, 0x01 },
	{ 0x3807, 0xeb },
	{ 0x3808, 0x02 }, /* width high */
	{ 0x3809, 0x80 }, /* width low */
	{ 0x380a, 0x01 }, /* height high */
	{ 0x380b, 0xe0 }, /* height low */
	{ 0x380c, 0x03 }, /* total horiz timing high */
	{ 0x380d, 0xa0 }, /* total horiz timing low */
	{ 0x380e, 0x03 }, /* total vertical timing high */
	{ 0x380f, 0x5c }, /* total vertical timing low */
	{ 0x3810, 0x00 },
	{ 0x3811, 0x04 },
	{ 0x3812, 0x00 },
	{ 0x3813, 0x05 },
	{ 0x3814, 0x11 },
	{ 0x3815, 0x11 },
	{ 0x3820, 0x40 },
	{ 0x3821, 0x00 },
	{ 0x382f, 0x0e },
	{ 0x3832, 0x00 },
	{ 0x3833, 0x05 },
	{ 0x3834, 0x00 },
	{ 0x3835, 0x0c },
	{ 0x3837, 0x00 },
	{ 0x3b80, 0x00 },
	{ 0x3b81, 0xa5 },
	{ 0x3b82, 0x10 },
	{ 0x3b83, 0x00 },
	{ 0x3b84, 0x08 },
	{ 0x3b85, 0x00 },
	{ 0x3b86, 0x01 },
	{ 0x3b87, 0x00 },
	{ 0x3b88, 0x00 },
	{ 0x3b89, 0x00 },
	{ 0x3b8a, 0x00 },
	{ 0x3b8b, 0x05 },
	{ 0x3b8c, 0x00 },
	{ 0x3b8d, 0x00 },
	{ 0x3b8e, 0x00 },
	{ 0x3b8f, 0x1a },
	{ 0x3b94, 0x05 },
	{ 0x3b95, 0xf2 },
	{ 0x3b96, 0x40 },
	{ 0x3c00, 0x89 },
	{ 0x3c01, 0x63 },
	{ 0x3c02, 0x01 },
	{ 0x3c03, 0x00 },
	{ 0x3c04, 0x00 },
	{ 0x3c05, 0x03 },
	{ 0x3c06, 0x00 },
	{ 0x3c07, 0x06 },
	{ 0x3c0c, 0x01 },
	{ 0x3c0d, 0xd0 },
	{ 0x3c0e, 0x02 },
	{ 0x3c0f, 0x0a },
	{ 0x4001, 0x42 },
	{ 0x4004, 0x04 },
	{ 0x4005, 0x00 },
	{ 0x404e, 0x01 },
	{ 0x4300, 0xff },
	{ 0x4301, 0x00 },
	{ 0x4315, 0x00 },
	{ 0x4501, 0x48 },
	{ 0x4600, 0x00 },
	{