// SPDX-License-Identifier: GPL-2.0-only
/*
* Omnivision OV9650/OV9652 CMOS Image Sensor driver
*
* Copyright (C) 2013, Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
*
* Register definitions and initial settings based on a driver written
* by Vladimir Fonov.
* Copyright (c) 2010, Vladimir Fonov
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/media.h>
#include <linux/module.h>
#include <linux/ratelimit.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/videodev2.h>
#include <media/media-entity.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-image-sizes.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-mediabus.h>
#include <media/i2c/ov9650.h>
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-2)");
#define DRIVER_NAME "OV9650"
/*
* OV9650/OV9652 register definitions
*/
#define REG_GAIN 0x00 /* Gain control, AGC[7:0] */
#define REG_BLUE 0x01 /* AWB - Blue channel gain */
#define REG_RED 0x02 /* AWB - Red channel gain */
#define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */
#define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */
#define REG_COM1 0x04
#define COM1_CCIR656 0x40
#define REG_B_AVE 0x05
#define REG_GB_AVE 0x06
#define REG_GR_AVE 0x07
#define REG_R_AVE 0x08
#define REG_COM2 0x09
#define REG_PID 0x0a /* Product ID MSB */
#define REG_VER 0x0b /* Product ID LSB */
#define REG_COM3 0x0c
#define COM3_SWAP 0x40
#define COM3_VARIOPIXEL1 0x04
#define REG_COM4 0x0d /* Vario Pixels */
#define COM4_VARIOPIXEL2 0x80
#define REG_COM5 0x0e /* System clock options */
#define COM5_SLAVE_MODE 0x10
#define COM5_SYSTEMCLOCK48MHZ 0x80
#define REG_COM6 0x0f /* HREF & ADBLC options */
#define REG_AECH 0x10 /* Exposure value, AEC[9:2] */
#define REG_CLKRC 0x11 /* Clock control */
#define CLK_EXT 0x40 /* Use external clock directly */
#define CLK_SCALE 0x3f /* Mask for internal clock scale */
#define REG_COM7 0x12 /* SCCB reset, output format */
#define COM7_RESET 0x80
#define COM7_FMT_MASK 0x38
#define COM7_FMT_VGA 0x40
#define COM7_FMT_CIF 0x20
#define COM7_FMT_QVGA 0x10
#define COM7_FMT_QCIF 0x08
#define COM7_RGB 0x04
#define COM7_YUV 0x00
#define COM7_BAYER 0x01
#define COM7_PBAYER 0x05
#define REG_COM8 0x13 /* AGC/AEC options */
#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
#define COM8_BFILT 0x20 /* Band filter enable */
#define COM8_AGC 0x04 /* Auto gain enable */
#define COM8_AWB 0x02 /* White balance enable */
#define COM8_AEC 0x01 /* Auto exposure enable */
#define REG_COM9 0x14 /* Gain ceiling */
#define COM9_GAIN_CEIL_MASK 0x70 /* */
#define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */
#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
#define COM10_HREF_REV 0x08 /* Reverse HREF */
#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
#define COM10_VS_NEG 0x02 /* VSYNC negative */
#define COM10_HS_NEG 0x01 /* HSYNC negative */
#define REG_HSTART 0x17 /* Horiz start high bits */
#define REG_HSTOP 0x18 /* Horiz stop high bits */
#define REG_VSTART 0x19 /* Vert start high bits */
#define REG_VSTOP 0x1a /* Vert stop high bits */
#define REG_PSHFT 0x1b /* Pixel delay after HREF */
#define REG_MIDH 0x1c /* Manufacturer ID MSB */
#define REG_MIDL 0x1d /* Manufufacturer ID LSB */
#define REG_MVFP 0x1e /* Image mirror/flip */
#define MVFP_MIRROR 0x20 /* Mirror image */
#define MVFP_FLIP 0x10 /* Vertical flip */
#def
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