/*
* Driver for STM32 Digital Camera Memory Interface
*
* Copyright (C) STMicroelectronics SA 2017
* Authors: Yannick Fertre <yannick.fertre@st.com>
* Hugues Fruchet <hugues.fruchet@st.com>
* for STMicroelectronics.
* License terms: GNU General Public License (GPL), version 2
*
* This driver is based on atmel_isi.c
*
*/
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/videodev2.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-image-sizes.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-of.h>
#include <media/videobuf2-dma-contig.h>
#define DRV_NAME "stm32-dcmi"
/* Registers offset for DCMI */
#define DCMI_CR 0x00 /* Control Register */
#define DCMI_SR 0x04 /* Status Register */
#define DCMI_RIS 0x08 /* Raw Interrupt Status register */
#define DCMI_IER 0x0C /* Interrupt Enable Register */
#define DCMI_MIS 0x10 /* Masked Interrupt Status register */
#define DCMI_ICR 0x14 /* Interrupt Clear Register */
#define DCMI_ESCR 0x18 /* Embedded Synchronization Code Register */
#define DCMI_ESUR 0x1C /* Embedded Synchronization Unmask Register */
#define DCMI_CWSTRT 0x20 /* Crop Window STaRT */
#define DCMI_CWSIZE 0x24 /* Crop Window SIZE */
#define DCMI_DR 0x28 /* Data Register */
#define DCMI_IDR 0x2C /* IDentifier Register */
/* Bits definition for control register (DCMI_CR) */
#define CR_CAPTURE BIT(0)
#define CR_CM BIT(1)
#define CR_CROP BIT(2)
#define CR_JPEG BIT(3)
#define CR_ESS BIT(4)
#define CR_PCKPOL BIT(5)
#define CR_HSPOL BIT(6)
#define CR_VSPOL BIT(7)
#define CR_FCRC_0 BIT(8)
#define CR_FCRC_1 BIT(9)
#define CR_EDM_0 BIT(10)
#define CR_EDM_1 BIT(11)
#define CR_ENABLE BIT(14)
/* Bits definition for status register (DCMI_SR) */
#define SR_HSYNC BIT(0)
#define SR_VSYNC BIT(1)
#define SR_FNE BIT(2)
/*
* Bits definition for interrupt registers
* (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR)
*/
#define IT_FRAME BIT(0)
#define IT_OVR BIT(1)
#define IT_ERR BIT(2)
#define IT_VSYNC BIT(3)
#define IT_LINE BIT(4)
enum state {
STOPPED = 0,
RUNNING,
STOPPING,
};
#define MIN_WIDTH 16U
#define MAX_WIDTH 2048U
#define MIN_HEIGHT 16U
#define MAX_HEIGHT 2048U
#define TIMEOUT_MS 1000
struct dcmi_graph_entity {
struct device_node *node;
struct v4l2_async_subdev asd;
struct v4l2_subdev *subdev;
};
struct dcmi_format {
u32 fourcc;
u32 mbus_code;
u8