// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Rockchip NAND Flash controller driver.
* Copyright (C) 2020 Rockchip Inc.
* Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
/*
* NFC Page Data Layout:
* 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
* 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
* ......
* NAND Page Data Layout:
* 1024 * n data + m Bytes oob
* Original Bad Block Mask Location:
* First byte of oob(spare).
* nand_chip->oob_poi data layout:
* 4Bytes sys data + .... + 4Bytes sys data + ECC data.
*/
/* NAND controller register definition */
#define NFC_READ (0)
#define NFC_WRITE (1)
#define NFC_FMCTL (0x00)
#define FMCTL_CE_SEL_M 0xFF
#define FMCTL_CE_SEL(x) (1 << (x))
#define FMCTL_WP BIT(8)
#define FMCTL_RDY BIT(9)
#define NFC_FMWAIT (0x04)
#define FLCTL_RST BIT(0)
#define FLCTL_WR (1) /* 0: read, 1: write */
#define FLCTL_XFER_ST BIT(2)
#define FLCTL_XFER_EN BIT(3)
#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */
#define FLCTL_XFER_READY BIT(20)
#define FLCTL_XFER_SECTOR (22)
#define FLCTL_TOG_FIX BIT(29)
#define BCHCTL_BANK_M (7 << 5)
#define BCHCTL_BANK (5)
#define DMA_ST BIT(0)
#define DMA_WR (1) /* 0: write, 1: read */
#define DMA_EN BIT(2)
#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */
#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */
#define DMA_INC_NUM (9) /* 1 - 16 */
#define ECC_ERR_CNT(x, e) ((((x) >
