path: root/drivers/net/can/at91_can.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91_can.c - CAN network driver for AT91 SoC CAN controller
 *
 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
 * (C) 2008, 2009, 2010, 2011, 2023 by Marc Kleine-Budde <kernel@pengutronix.de>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/ethtool.h>
#include <linux/if_arp.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/rtnetlink.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>

#include <linux/can/dev.h>
#include <linux/can/error.h>
#include <linux/can/rx-offload.h>

#define AT91_MB_MASK(i) ((1 << (i)) - 1)

/* Common registers */
enum at91_reg {
	AT91_MR = 0x000,
	AT91_IER = 0x004,
	AT91_IDR = 0x008,
	AT91_IMR = 0x00C,
	AT91_SR = 0x010,
	AT91_BR = 0x014,
	AT91_TIM = 0x018,
	AT91_TIMESTP = 0x01C,
	AT91_ECR = 0x020,
	AT91_TCR = 0x024,
	AT91_ACR = 0x028,
};

/* Mailbox registers (0 <= i <= 15) */
#define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20)))
#define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20)))
#define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20)))
#define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20)))
#define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20)))
#define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20)))
#define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20)))
#define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20)))

/* Register bits */
#define AT91_MR_CANEN BIT(0)
#define AT91_MR_LPM BIT(1)
#define AT91_MR_ABM BIT(2)
#define AT91_MR_OVL BIT(3)
#define AT91_MR_TEOF BIT(4)
#define AT91_MR_TTM BIT(5)
#define AT91_MR_TIMFRZ BIT(6)
#define AT91_MR_DRPT BIT(7)

#define AT91_SR_RBSY BIT(29)
#define AT91_SR_TBSY BIT(30)
#define AT91_SR_OVLSY BIT(31)

#define AT91_BR_PHASE2_MASK GENMASK(2, 0)
#define AT91_BR_PHASE1_MASK GENMASK(6, 4)
#define AT91_BR_PROPAG_MASK GENMASK(10, 8)
#define AT91_BR_SJW_MASK GENMASK(13, 12)
#define AT91_BR_BRP_MASK GENMASK(22, 16)
#define AT91_BR_SMP BIT(24)

#define AT91_TIM_TIMER_MASK GENMASK(15, 0)

#define AT91_ECR_REC_MASK GENMASK(8, 0)
#define AT91_ECR_TEC_MASK GENMASK(23, 16)

#define AT91_TCR_TIMRST BIT(31)

#define AT91_MMR_MTIMEMARK_MASK GENMASK(15, 0)
#define AT91_MMR_PRIOR_MASK GENMASK(19, 16)
#define AT91_MMR_MOT_MASK GENMASK(26, 24)

#define AT91_MID_MIDVB_MASK GENMASK(17, 0)
#define AT91_MID_MIDVA_MASK GENMASK(28, 18)
#define AT91_MID_MIDE BIT(29)

#define AT91_MSR_MTIMESTAMP_MASK GENMASK(15, 0)
#define AT91_MSR_MDLC_MASK GENMASK(19, 16)
#define AT91_MSR_MRTR BIT(20)
#define AT91_MSR_MABT BIT(22)
#define AT91_MSR_MRDY BIT(23)
#define AT91_MSR_MMI BIT(24)

#define AT91_MCR_MDLC_MASK GENMASK(19, 16)
#define AT91_MCR_MRTR BIT(20)
#define AT91_MCR_MACR BIT(22)
#define AT91_MCR_MTCR BIT(23)

/* Mailbox Modes */
enum at91_mb_mode {
	AT91_MB_MODE_DISABLED = 0,
	AT91_MB_MODE_RX = 1,
	AT91_MB_MODE_RX_OVRWR = 2,
	AT91_MB_MODE_TX = 3,
	AT91_MB_MODE_CONSUMER = 4,
	AT91_MB_MODE_PRODUCER = 5,
};

/* Interrupt mask bits */
#define AT91_IRQ_ERRA BIT(16)
#define AT91_IRQ_WARN BIT(17)
#define AT91_IRQ_ERRP BIT(18)
#define AT91_IRQ_BOFF BIT(19)
#define AT91_IRQ_SLEEP BIT(20)
#define AT91_IRQ_WAKEUP BIT(21)
#define AT91_IRQ_TOVF BIT(22)
#define AT91_IRQ_TSTP BIT(23)
#define AT91_IRQ_CERR BIT(24)
#define AT91_IRQ_SERR BIT(25)
#define AT91_IRQ_AERR BIT(26)
#define AT91_IRQ_FERR BIT(27)
#define AT91_IRQ_BERR BIT(28)

#define AT91_IRQ_ERR_ALL (0x1fff0000)
#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
			    AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
			   AT91_IRQ_ERRP | AT91_IRQ_BOFF)

#define AT91_IRQ_ALL (0x1fffffff)

enum at91_devtype {
	AT91_DEVTYPE_SAM9263,
	AT91_DEVTYPE_SAM9X5,
};

struct at91_devtype_data {
	unsigned int rx_first;
	unsigned int rx_last;
	unsigned int tx_shift;
	enum at91_devtype type;
};

struct at91_priv {
	struct can_priv can;		/* must be the first member! */
	struct can_rx_offload offload;
	struct phy *transceiver;

	void __iomem *reg_base;

	unsigned int tx_head;
	unsigned int tx_tail;
	struct at91_devtype_data devtype_data;

	struct clk *clk;
	struct at91_can_data *pdata;

	canid_t mb0_id;
};

static inline struct at91_priv *rx_offload_to_priv(struct can_rx_offload *offload)
{
	return container_of(offload, struct at91_priv, offload);
}

static const struct at91_devtype_data at91_at91sam9263_data = {
	.rx_first = 1,
	.rx_last = 11,
	.tx_shift = 2,
	.type = AT91_DEVTYPE_SAM9263,
};

static const struct at91_devtype_data at91_at91sam9x5_data = {
	.rx_first = 0,
	.rx_last = 5,
	.tx_shift = 1,
	.type = AT91_DEVTYPE_SAM9X5,
};

static const struct can_bittiming_const at91_bittiming_const = {
	.name		= KBUILD_MODNAME,
	.tseg1_min	= 4,
	.tseg1_max	= 16,
	.tseg2_min	= 2,
	.tseg2_max	= 8,
	.sjw_max	= 4,
	.brp_min	= 2,
	.brp_max	= 128,
	.brp_inc	= 1,
};