path: root/drivers/net/dsa/microchip/ksz9477_reg.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Microchip KSZ9477 register definitions
 *
 * Copyright (C) 2017-2018 Microchip Technology Inc.
 */

#ifndef __KSZ9477_REGS_H
#define __KSZ9477_REGS_H

#define KS_PRIO_M			0x7
#define KS_PRIO_S			4

/* 0 - Operation */
#define REG_CHIP_ID0__1			0x0000

#define REG_CHIP_ID1__1			0x0001

#define FAMILY_ID			0x95
#define FAMILY_ID_94			0x94
#define FAMILY_ID_95			0x95
#define FAMILY_ID_85			0x85
#define FAMILY_ID_98			0x98
#define FAMILY_ID_88			0x88

#define REG_CHIP_ID2__1			0x0002

#define CHIP_ID_66			0x66
#define CHIP_ID_67			0x67
#define CHIP_ID_77			0x77
#define CHIP_ID_93			0x93
#define CHIP_ID_96			0x96
#define CHIP_ID_97			0x97

#define REG_CHIP_ID3__1			0x0003

#define SWITCH_REVISION_M		0x0F
#define SWITCH_REVISION_S		4
#define SWITCH_RESET			0x01

#define REG_SW_PME_CTRL			0x0006

#define PME_ENABLE			BIT(1)
#define PME_POLARITY			BIT(0)

#define REG_GLOBAL_OPTIONS		0x000F

#define SW_GIGABIT_ABLE			BIT(6)
#define SW_REDUNDANCY_ABLE		BIT(5)
#define SW_AVB_ABLE			BIT(4)
#define SW_9567_RL_5_2			0xC
#define SW_9477_SL_5_2			0xD

#define SW_9896_GL_5_1			0xB
#define SW_9896_RL_5_1			0x8
#define SW_9896_SL_5_1			0x9

#define SW_9895_GL_4_1			0x7
#define SW_9895_RL_4_1			0x4
#define SW_9895_SL_4_1			0x5

#define SW_9896_RL_4_2			0x6

#define SW_9893_RL_2_1			0x0
#define SW_9893_SL_2_1			0x1
#define SW_9893_GL_2_1			0x3

#define SW_QW_ABLE			BIT(5)
#define SW_9893_RN_2_1			0xC

#define REG_SW_INT_STATUS__4		0x0010
#define REG_SW_INT_MASK__4		0x0014

#define LUE_INT				BIT(31)
#define TRIG_TS_INT			BIT(30)
#define APB_TIMEOUT_INT			BIT(29)

#define SWITCH_INT_MASK			(TRIG_TS_INT | APB_TIMEOUT_INT)

#define REG_SW_PORT_INT_STATUS__4	0x0018
#define REG_SW_PORT_INT_MASK__4		0x001C
#define REG_SW_PHY_INT_STATUS		0x0020
#define REG_SW_PHY_INT_ENABLE		0x0024

/* 1 - Global */
#define REG_SW_GLOBAL_SERIAL_CTRL_0	0x0100
#define SW_SPARE_REG_2			BIT(7)
#define SW_SPARE_REG_1			BIT(6)
#define SW_SPARE_REG_0			BIT(5)
#define SW_BIG_ENDIAN			BIT(4)
#define SPI_AUTO_EDGE_DETECTION		BIT(1)
#define SPI_CLOCK_OUT_RISING_EDGE	BIT(0)

#define REG_SW_GLOBAL_OUTPUT_CTRL__1	0x0103
#define SW_ENABLE_REFCLKO		BIT(1)
#define SW_REFCLKO_IS_125MHZ		BIT(0)

#define REG_SW_IBA__4			0x0104

#define SW_IBA_ENABLE			BIT(31)
#define SW_IBA_DA_MATCH			BIT(30)
#define SW_IBA_INIT			BIT(29)
#define SW_IBA_QID_M			0xF
#define SW_IBA_QID_S			22
#define SW_IBA_PORT_M			0x2F
#define SW_IBA_PORT_S			16
#define SW_IBA_FRAME_TPID_M		0xFFFF

#define REG_SW_APB_TIMEOUT_ADDR__4	0x0108

#define APB_TIMEOUT_ACKNOWLEDGE		BIT(31)

#define REG_SW_IBA_SYNC__1		0x010C

#define REG_SW_IBA_STATUS__4		0x0110

#define SW_IBA_REQ			BIT(31)
#define SW_IBA_RESP			BIT(30)
#define SW_IBA_DA_MISMATCH		BIT(14)
#define SW_IBA_FMT_MISMATCH		BIT(13)
#define SW_IBA_CODE_ERROR		BIT(12)
#define SW_IBA_CMD_ERROR		BIT(11)
#define SW_IBA_CMD_LOC_M		(BIT(6) - 1)

#define REG_SW_IBA_STATES__4		0x0114

#define SW_IBA_BUF_STATE_S		30
#define SW_IBA_CMD_STATE_S		28
#define SW_IBA_RESP_STATE_S		26
#define SW_IBA_STATE_M			0x3
#define SW_IBA_PACKET_SIZE_M		0x7F
#define SW_IBA_PACKET_SIZE_S		16
#define SW_IBA_FMT_ID_M			0xFFFF

#define REG_SW_IBA_RESULT__4		0x0118

#define SW_IBA_SIZE_S			24

#define SW_IBA_RETRY_CNT_M		(BIT(5) - 1)

/* 2 - PHY */
#define REG_SW_POWER_MANAGEMENT_CTRL	0x0201

#define SW_PLL_POWER_DOWN		BIT(5)
#define SW_POWER_DOWN_MODE		0x3
#define SW_ENERGY_DETECTION		1
#define SW_SOFT_POWER_DOWN		2
#define SW_POWER_SAVING			3

/* 3 - Operation Control */
#define REG_SW_OPERATION		0x0300

#define SW_DOUBLE_TAG			BIT(7)
#define SW_RESET			BIT(1)

#define REG_SW_MTU__2			0x0308
#define REG_SW_MTU_MASK			GENMASK(13, 0)

#define REG_SW_ISP_TPID__2		0x030A

#define REG_SW_HSR_TPID__2		0x030C

#define REG_AVB_STRATEGY__2		0x030E

#define SW_SHAPING_CREDIT_ACCT		BIT(1)
#define SW_POLICING_CREDIT_ACCT		BIT(0)

#define REG_SW_LUE_CTRL_0		0x0310

#define SW_VLAN_ENABLE			BIT(7)
#define SW_DROP_INVALID_VID		BIT(6)
#define SW_AGE_CNT_M			GENMASK(5, 3)
#define SW_AGE_CNT_S			3
#define SW_AGE_PERIOD_10_8_M		GENMASK(10, 8)
#define SW_RESV_MCAST_ENABLE		BIT(2)
#define SW_HASH_OPTION_M		0x03
#define SW_HASH_OPTION_CRC		1
#define SW_HASH_OPTION_XOR		2
#define SW_HASH_OPTION_DIRECT		3

#define REG_SW_LUE_CTRL_1		0x0311

#define UNICAST_LEARN_DISABLE		BIT(7)
#define SW_SRC_ADDR_FILTER		BIT(6)
#define SW_FLUSH_STP_TABLE		BIT(5)
#define SW_FLUSH_MSTP_TABLE		BIT(4)
#define SW_FWD_MCAST_SRC_ADDR		BIT(3)
#define SW_AGING_ENABLE			BIT(2)
#define SW_FAST_AGING			BIT(1)
#define SW_LINK_AUTO_AGING		BIT(0)

#define REG_SW_LUE_CTRL_2		0x0312

#define SW_TRAP_DOUBLE_TAG		BIT(6)
#define SW_EGRESS_VLAN_FILTER_DYN	BIT(5)
#define SW_EGRESS_VLAN_FILTER_STA	BIT(4)
#define SW_FLUSH_OPTION_M		0x3
#define SW_FLUSH_OPTION_S		2
#define SW_FLUSH_OPTION_DYN_MAC		1
#define SW_FLUSH_OPTION_STA_MAC		2
#define SW_FLUSH_OPTION_BOTH		3
#define SW_PRIO_M			0x3
#define SW_PRIO_DA			0
#define SW_PRIO_SA			1
#define SW_PRIO_HIGHEST_DA_SA		2
#define SW_PRIO_LOWEST_DA_SA		3

#define REG_SW_LUE_CTRL_3		0x0313
#define SW_AGE_PERIOD_7_0_M		GENMASK(7, 0)

#define REG_SW_LUE_INT_STATUS		0x0314
#define REG_SW_LUE_INT_ENABLE		0x0315

#define LEARN_FAIL_INT			BIT(2)
#define ALMOST_FULL_INT			BIT(1)
#define WRITE_FAIL_INT			BIT(0)

#define REG_SW_LUE_INDEX_0__2		0x0316

#define ENTRY_INDEX_M			0x0FFF

#define REG_SW_LUE_INDEX_1__2		0x0318

#define FAIL_INDEX