path: root/drivers/net/ethernet/microchip/lan743x_main.h

/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2018 Microchip Technology Inc. */

#ifndef _LAN743X_H
#define _LAN743X_H

#include <linux/phy.h>
#include <linux/phylink.h>
#include "lan743x_ptp.h"

#define DRIVER_AUTHOR   "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
#define DRIVER_NAME "lan743x"

/* Register Definitions */
#define ID_REV				(0x00)
#define ID_REV_ID_MASK_			(0xFFFF0000)
#define ID_REV_ID_LAN7430_		(0x74300000)
#define ID_REV_ID_LAN7431_		(0x74310000)
#define ID_REV_ID_LAN743X_		(0x74300000)
#define ID_REV_ID_A011_			(0xA0110000)	// PCI11010
#define ID_REV_ID_A041_			(0xA0410000)	// PCI11414
#define ID_REV_ID_A0X1_			(0xA0010000)
#define ID_REV_IS_VALID_CHIP_ID_(id_rev)	    \
	((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
	 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
#define ID_REV_CHIP_REV_MASK_		(0x0000FFFF)
#define ID_REV_CHIP_REV_A0_		(0x00000000)
#define ID_REV_CHIP_REV_B0_		(0x00000010)
#define ID_REV_CHIP_REV_PCI11X1X_B0_	(0x000000B0)

#define FPGA_REV			(0x04)
#define FPGA_REV_GET_MINOR_(fpga_rev)	(((fpga_rev) >> 8) & 0x000000FF)
#define FPGA_REV_GET_MAJOR_(fpga_rev)	((fpga_rev) & 0x000000FF)
#define FPGA_SGMII_OP			BIT(24)

#define STRAP_READ			(0x0C)
#define STRAP_READ_USE_SGMII_EN_	BIT(22)
#define STRAP_READ_SGMII_EN_		BIT(6)
#define STRAP_READ_SGMII_REFCLK_	BIT(5)
#define STRAP_READ_SGMII_2_5G_		BIT(4)
#define STRAP_READ_BASE_X_		BIT(3)
#define STRAP_READ_RGMII_TXC_DELAY_EN_	BIT(2)
#define STRAP_READ_RGMII_RXC_DELAY_EN_	BIT(1)
#define STRAP_READ_ADV_PM_DISABLE_	BIT(0)

#define HW_CFG					(0x010)
#define HW_CFG_RST_PROTECT_PCIE_		BIT(19)
#define HW_CFG_HOT_RESET_DIS_			BIT(15)
#define HW_CFG_D3_VAUX_OVR_			BIT(14)
#define HW_CFG_D3_RESET_DIS_			BIT(13)
#define HW_CFG_RST_PROTECT_			BIT(12)
#define HW_CFG_RELOAD_TYPE_ALL_			(0x00000FC0)
#define HW_CFG_EE_OTP_RELOAD_			BIT(4)
#define HW_CFG_LRST_				BIT(1)

#define PMT_CTL					(0x014)
#define PMT_CTL_ETH_PHY_D3_COLD_OVR_		BIT(27)
#define PMT_CTL_MAC_D3_RX_CLK_OVR_		BIT(25)
#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_		BIT(24)
#define PMT_CTL_ETH_PHY_D3_OVR_			BIT(23)
#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_		BIT(18)
#define PMT_CTL_GPIO_WAKEUP_EN_			BIT(15)
#define PMT_CTL_EEE_WAKEUP_EN_			BIT(13)
#define PMT_CTL_RES_CLR_WKP_MASK_		GENMASK(9, 8)
#define PMT_CTL_READY_				BIT(7)
#define PMT_CTL_ETH_PHY_RST_			BIT(4)
#define PMT_CTL_WOL_EN_				BIT(3)
#define PMT_CTL_ETH_PHY_WAKE_EN_		BIT(2)
#define PMT_CTL_WUPS_MASK_			(0x00000003)

#define DP_SEL				(0x024)
#define DP_SEL_DPRDY_			BIT(31)
#define DP_SEL_MASK_			(0x0000001F)
#define DP_SEL_RFE_RAM			(0x00000001)

#define DP_SEL_VHF_HASH_LEN		(16)
#define DP_SEL_VHF_VLAN_LEN		(128)

#define DP_CMD				(0x028)
#define DP_CMD_WRITE_			(0x00000001)

#define DP_ADDR				(0x02C)

#define DP_DATA_0			(0x030)

#define E2P_CMD				(0x040)
#define E2P_CMD_EPC_BUSY_		BIT(31)
#define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
#define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
#define E2P_CMD_EPC_CMD_READ_		(0x00000000)
#define E2P_CMD_EPC_TIMEOUT_		BIT(10)
#define E2P_CMD_EPC_ADDR_MASK_		(0x000001FF)

#define E2P_DATA			(0x044)

/* Hearthstone top level & System Reg Addresses */
#define ETH_CTRL_REG_ADDR_BASE		(0x0000)
#define ETH_SYS_REG_ADDR_BASE		(0x4000)
#define CONFIG_REG_ADDR_BASE		(0x0000)
#define ETH_EEPROM_REG_ADDR_BASE	(0x0E00)
#define ETH_OTP_REG_ADDR_BASE		(0x1000)
#define GEN_SYS_CONFIG_LOAD_STARTED_REG	(0x0078)
#define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \
					 CONFIG_REG_ADDR_BASE + \
					 GEN_SYS_CONFIG_LOAD_STARTED_REG)
#define GEN_SYS_LOAD_STARTED_REG_ETH_	BIT(4)
#define SYS_LOCK_REG			(0x00A0)
#define SYS_LOCK_REG_MAIN_LOCK_		BIT(7)
#define SYS_LOCK_REG_GEN_PERI_LOCK_	BIT(5)
#define SYS_LOCK_REG_SPI_PERI_LOCK_	BIT(4)
#define SYS_LOCK_REG_SMBUS_PERI_LOCK_	BIT(3)
#define SYS_LOCK_REG_UART_SS_LOCK_	BIT(2)
#define SYS_LOCK_REG_ENET_SS_LOCK_	BIT(1)
#define SYS_LOCK_REG_USB_SS_LOCK_	BIT(0)
#define ETH_SYSTEM_SYS_LOCK_REG		(ETH_SYS_REG_ADDR_BASE + \
					 CONFIG_REG_ADDR_BASE + \
					 SYS_LOCK_REG)
#define HS_EEPROM_REG_ADDR_BASE		(ETH_SYS_REG_ADDR_BASE + \
					 ETH_EEPROM_REG_ADDR_BASE)
#define HS_E2P_CMD			(HS_EEPROM_REG_ADDR_BASE + 0x0000)
#define HS_E2P_CMD_EPC_BUSY_		BIT(31)
#define HS_E2P_CMD_EPC_CMD_WRITE_	GENMASK(29, 28)
#define HS_E2P_CMD_EPC_CMD_READ_	(0x0)
#define HS_E2P_CMD_EPC_TIMEOUT_		BIT(17)
#define HS_E2P_CMD_EPC_ADDR_MASK_	GENMASK(15, 0)
#define HS_E2P_DATA			(HS_EEPROM_REG_ADDR_BASE + 0x0004)
#define HS_E2P_DATA_MASK_		GENMASK(7, 0)
#define HS_E2P_CFG			(HS_EEPROM_REG_ADDR_BASE + 0x0008)
#define HS_E2P_CFG_I2C_PULSE_MASK_	GENMASK(19, 16)
#define HS_E2P_CFG_EEPROM_SIZE_SEL_	BIT(12)
#define HS_E2P_CFG_I2C_BAUD_RATE_MASK_	GENMASK(9, 8)
#define HS_E2P_CFG_TEST_EEPR_TO_BYP_	BIT(0)
#define HS_E2P_PAD_CTL			(HS_EEPROM_REG_ADDR_BASE + 0x000C)

#define GPIO_CFG0			(0x050)
#define GPIO_CFG0_GPIO_DIR_BIT_(bit)	BIT(16 + (bit))
#define GPIO_CFG0_GPIO_DATA_BIT_(bit)	BIT(0 + (bit))

#define GPIO_CFG1			(0x054)
#define GPIO_CFG1_GPIOEN_BIT_(bit)	BIT(16 + (bit))
#define GPIO_CFG1_GPIOBUF_BIT_(bit)	BIT(0 + (bit))

#define GPIO_CFG2			(0x058)
#define GPIO_CFG2_1588_POL_BIT_(bit)	BIT(0 + (bit))

#define GPIO_CFG3			(0x05C)
#define GPIO_CFG3_1588_CH_SEL_BIT_(bit)	BIT(16 + (bit))
#define GPIO_CFG3_1588_OE_BIT_(bit)	BIT(0 + (bit))

#define FCT_RX_CTL			(0xAC)
#define FCT_RX_CTL_EN_(channel)		BIT(28 + (channel))
#define FCT_RX_CTL_DIS_(channel)	BIT(24 + (channel))
#define FCT_RX_CTL_RESET_(channel)	BIT(20 + (channel))

#define FCT_TX_CTL			(0xC4)
#define FCT_TX_CTL_EN_(channel)		BIT(28 + (channel))
#define FCT_TX_CTL_DIS_(channel)	BIT(24 + (channel))
#define FCT_TX_CTL_RESET_(channel)	BIT(20 + (channel))

#define FCT_FLOW(rx_channel)			(0xE0 + ((rx_channel) << 2))
#define FCT_FLOW_CTL_OFF_THRESHOLD_		(0x00007F00)
#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value)	\
	((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
#define FCT_FLOW_CTL_REQ_EN_			BIT(7)
#define FCT_FLOW_CTL_ON_THRESHOLD_		(0x0000007F)
#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value)	\
	((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)

#define MAC_CR				(0x100)
#define MAC_CR_MII_EN_			BIT(19)
#define MAC_CR_EEE_EN_			BIT(17)
#define MAC_CR_ADD_			BIT(12)
#define MAC_CR_ASD_			BIT(11)
#define MAC_CR_CNTR_RST_		BIT(5)
#define MAC_CR_DPX_			BIT(3)
#define MAC_CR_CFG_H_			BIT(2)
#define MAC_CR_CFG_L_			BIT(1)
#define MAC_CR_RST_			BIT(0)

#define MAC_RX				(0x104)
#define MAC_RX_MAX_SIZE_SHIFT_		(16)
#define MAC_RX_MAX_SIZE_MASK_		(0x3FFF0000)
#define MAC_RX_RXD_			BIT(1)
#define MAC_RX_RXEN_			BIT(0)

#define MAC_TX				(0x108)
#define MAC_TX_TXD_			BIT(1)
#define MAC_TX_TXEN_			BIT(0)

#define MAC_FLOW			(0x10C)
#define MAC_FLOW_CR_TX_FCEN_		BIT(30)
#define MAC_FLOW_CR_RX_FCEN_		BIT(29)
#define MAC_FLOW_CR_FCPT_MASK_		(0x0000FFFF)

#define MAC_RX_ADDRH			(0x118)

#define MAC_RX_ADDRL			(0x11C)

#define MAC_MII_ACC			(0x120)
#define MAC_MII_ACC_MDC_CYCLE_SHIFT_	(16)
#define MAC_MII_ACC_MDC_CYCLE_MASK_	(0x00070000)
#define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_	(0)
#define MAC_MII_ACC_MDC_CYCLE_5MHZ_	(1)
#define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_	(2)
#define MAC_MII_ACC_MDC_CYCLE_25MHZ_	(3)
#define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_	(4)
#define MAC_MII_ACC_PHY_ADDR_SHIFT_	(11)
#define MAC_MII_ACC_PHY_ADDR_MASK_	(0x0000F800)
#define MAC_MII_ACC_MIIRINDA_SHIFT_	(6)
#define MAC_MII_ACC_MIIRINDA_MASK_	(0x000007C0)
#define MAC_MII_ACC_MII_READ_		(0x00000000)
#define MAC_MII_ACC_MII_WRITE_		(0x00000002)
#define MAC_MII_ACC_MII_BUSY_		BIT(0)

#define MAC_MII_ACC_MIIMMD_SHIFT_	(6)
#define MAC_MII_ACC_MIIMMD_MASK_	(0x000007C0)
#define MAC_MII_ACC_MIICL45_		BIT(3)
#define MAC_MII_ACC_MIICMD_MASK_	(0x00000006)
#define MAC_MII_ACC_MIICMD_ADDR_	(0x00000000)
#define MAC_MII_ACC_MIICMD_WRITE_	(0x00000002)
#define MAC_MII_ACC_MIICMD_READ_	(0x00000004)
#define MAC_MII_ACC_MIICMD_READ_INC_	(0x00000006)

#define MAC_MII_DATA			(0x124)

#define MAC_EEE_TX_LPI_REQ_DLY_CNT		(0x130)

#define MAC_WUCSR				(0x140)
#define MAC_MP_SO_EN_				BIT(21)
#define MAC_WUCSR_RFE_WAKE_EN_			BIT(14)
#define MAC_WUCSR_EEE_TX_WAKE_			BIT(13)
#define MAC_WUCSR_EEE_RX_WAKE_			BIT(11)
#define MAC_WUCSR_RFE_WAKE_FR_			BIT(9)
#define MAC_WUCSR_PFDA_FR_			BIT(7)
#define MAC_WUCSR_WUFR_				BIT(6)
#define MAC_WUCSR_MPR_				BIT(5)
#define MAC_WUCSR_BCAST_FR_			BIT(4)
#define MAC_WUCSR_PFDA_EN_			BIT(3)
#define MAC_WUCSR_WAKE_EN_			BIT(2)
#define MAC_WUCSR_MPEN_				BIT(1)
#define MAC_WUCSR_BCST_EN_			BIT(0)

#define MAC_WK_SRC				(0x144)
#define MAC_WK_SRC_ETH_PHY_WK_			BIT(17)
#define MAC_WK_SRC_IPV6_TCPSYN_RCD_WK_		BIT(16)
#define MAC_WK_SRC_IPV4_TCPSYN_RCD_WK_		BIT(15)
#define MAC_WK_SRC_EEE_TX_WK_			BIT(14)
#define MAC_WK_SRC_EEE_RX_WK_			BIT(13)
#define MAC_WK_SRC_RFE_FR_WK_			BIT(12)
#define MAC_WK_SRC_PFDA_FR_WK_			BIT(11)
#define MAC_WK_SRC_MP_FR_WK_			BIT(10)
#define MAC_WK_SRC_BCAST_FR_WK_			BIT(9)
#define MAC_WK_SRC_WU_FR_WK_			BIT(8)
#define MAC_WK_SRC_WK_FR_SAVED_			BIT(7)

#define MAC_MP_SO_HI				(0x148)
#define MAC_MP_SO_LO				(0x14C)

#define MAC_WUF_CFG0			(0x150)
#define MAC_NUM_OF_WUF_CFG		(32)
#define MAC_WUF_CFG_BEGIN		(MAC_WUF_CFG0)
#define MAC_WUF_CFG(index)		(MAC_WUF_CFG_BEGIN + (4 * (index)))
#define MAC_WUF_CFG_EN_			BIT(31)
#define MAC_WUF_CFG_TYPE_MCAST_		(0x02000000)
#define MAC_WUF_CFG_TYPE_ALL_		(0x01000000)
#define MAC_WUF_CFG_OFFSET_SHIFT_	(16)
#define MAC_WUF_CFG_CRC16_MASK_		(0x0000FFFF)

#define MAC_WUF_MASK0_0