path: root/drivers/net/ethernet/mscc/ocelot_hsio.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Microsemi Ocelot Switch driver
 *
 * Copyright (c) 2017 Microsemi Corporation
 */

#ifndef _MSCC_OCELOT_HSIO_H_
#define _MSCC_OCELOT_HSIO_H_

#define HSIO_PLL5G_CFG0_ENA_ROT                           BIT(31)
#define HSIO_PLL5G_CFG0_ENA_LANE                          BIT(30)
#define HSIO_PLL5G_CFG0_ENA_CLKTREE                       BIT(29)
#define HSIO_PLL5G_CFG0_DIV4                              BIT(28)
#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE                     BIT(27)
#define HSIO_PLL5G_CFG0_SELBGV820(x)                      (((x) << 23) & GENMASK(26, 23))
#define HSIO_PLL5G_CFG0_SELBGV820_M                       GENMASK(26, 23)
#define HSIO_PLL5G_CFG0_SELBGV820_X(x)                    (((x) & GENMASK(26, 23)) >> 23)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x)                    (((x) << 18) & GENMASK(22, 18))
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M                     GENMASK(22, 18)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x)                  (((x) & GENMASK(22, 18)) >> 18)
#define HSIO_PLL5G_CFG0_SELCPI(x)                         (((x) << 16) & GENMASK(17, 16))
#define HSIO_PLL5G_CFG0_SELCPI_M                          GENMASK(17, 16)
#define HSIO_PLL5G_CFG0_SELCPI_X(x)                       (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH                    BIT(15)
#define HSIO_PLL5G_CFG0_ENA_CP1                           BIT(14)
#define HSIO_PLL5G_CFG0_ENA_VCO_BUF                       BIT(13)
#define HSIO_PLL5G_CFG0_ENA_BIAS                          BIT(12)
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x)                    (((x) << 6) & GENMASK(11, 6))
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M                     GENMASK(11, 6)
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x)                  (((x) & GENMASK(11, 6)) >> 6)
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x)                   ((x) & GENMASK(5, 0))
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M                    GENMASK(5, 0)

#define HSIO_PLL5G_CFG1_ENA_DIRECT                        BIT(18)
#define HSIO_PLL5G_CFG1_ROT_SPEED                         BIT(17)
#define HSIO_PLL5G_CFG1_ROT_DIR                           BIT(16)
#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL                 BIT(15)
#define HSIO_PLL5G_CFG1_RC_ENABLE                         BIT(14)
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x)                   (((x) << 6) & GENMASK(13, 6))
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M                    GENMASK(13, 6)
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x)                 (((x) & GENMASK(13, 6)) >> 6)
#define HSIO_PLL5G_CFG1_QUARTER_RATE                      BIT(5)
#define HSIO_PLL5G_CFG1_PWD_TX                            BIT(4)
#define HSIO_PLL5G_CFG1_PWD_RX                            BIT(3)
#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA            BIT(2)
#define HSIO_PLL5G_CFG1_HALF_RATE                         BIT(1)
#define HSIO_PLL5G_CFG1_FORCE_SET_ENA                     BIT(0)

#define HSIO_PLL5G_CFG2_ENA_TEST_MODE                     BIT(30)
#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP                   BIT(29)
#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT              BIT(28)
#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT                     BIT(27)
#define HSIO_PLL5G_CFG2_ENA_RCPLL                         BIT(26)
#define HSIO_PLL5G_CFG2_ENA_CP2                           BIT(25)
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1                   BIT(24)
#define HSIO_PLL5G_CFG2_AMPC_SEL(x)                       (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG2_AMPC_SEL_M                        GENMASK(23, 16)
#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x)                     (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS                    BIT(15)
#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N                     BIT(14)
#define HSIO_PLL5G_CFG2_ENA_AMPCTRL                       BIT(13)
#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE                BIT(12)
#define HSIO_PLL5G_CFG2_FRC_FSM_POR                       BIT(11)
#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR                   BIT(10)
#define HSIO_PLL5G_CFG2_GAIN_TEST(x)                      (((x) << 5) & GENMASK(9, 5))
#define HSIO_PLL5G_CFG2_GAIN_TEST_M                       GENMASK(9, 5)
#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x)                    (((x) & GENMASK(9, 5)) >> 5)
#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN                  BIT(4)
#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET                  BIT(3)
#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET                  BIT(2)
#define HSIO_PLL5G_CFG2_DISABLE_FSM                       BIT(1)
#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST                     BIT(0)

#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x)               (((x) << 22) & GENMASK(23, 22))
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M                GENMASK(23, 22)
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x)             (((x) & GENMASK(23, 22)) >> 22)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x)                    (((x) << 19) & GENMASK(21, 19))
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M                     GENMASK(21, 19)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x)                  (((x) & GENMASK(21, 19)) >> 19)
#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT                  BIT(18)
#define HSIO_PLL5G_CFG3_ENA_TEST_OUT                      BIT(17)
#define HSIO_PLL5G_CFG3_SEL_FBDCLK                        BIT(16)
#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD                  BIT(15)
#define HSIO_PLL5G_CFG3_RST_FB_N                          BIT(14)
#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH                  BIT(13)
#define HSIO_PLL5G_CFG3_FORCE_LO                          BIT(12)
#define HSIO_PLL5G_CFG3_FORCE_HI                          BIT(11)
#define HSIO_PLL5G_CFG3_FORCE_ENA                         BIT(10)
#define HSIO_PLL5G_CFG3_FORCE_CP                          BIT(9)
#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA                  BIT(8)
#define HSIO_PLL5G_CFG3_FBDIVSEL(x)                       ((x) & GENMASK(7, 0))
#define HSIO_PLL5G_CFG3_FBDIVSEL_M                        GENMASK(7, 0)

#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x)                   (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M                    GENMASK(23, 16)
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x)                 (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG4_IB_CTRL(x)                        ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_CFG4_IB_CTRL_M                         GENMASK(15, 0)

#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x)                   (((x) << 16) & GENMASK(23, 16))
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M                    GENMASK(23, 16)
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x)                 (((x) & GENMASK(23, 16)) >> 16)
#define HSIO_PLL5G_CFG5_OB_CTRL(x)                        ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_CFG5_OB_CTRL_M                         GENMASK(15, 0)

#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC                    BIT(23)
#define HSIO_PLL5G_CFG6_REFCLK_SEL(x)                     (((x) << 20) & GENMASK(22, 20))
#define HSIO_PLL5G_CFG6_REFCLK_SEL_M                      GENMASK(22, 20)
#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x)                   (((x) & GENMASK(22, 20)) >> 20)
#define HSIO_PLL5G_CFG6_REFCLK_SRC                        BIT(19)
#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x)                    (((x) << 16) & GENMASK(17, 16))
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M                     GENMASK(17, 16)
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x)                  (((x) & GENMASK(17, 16)) >> 16)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x)                  (((x) << 8) & GENMASK(15, 8))
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M                   GENMASK(15, 8)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x)                (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_PLL5G_CFG6_ENA_REFCLKC2                      BIT(7)
#define HSIO_PLL5G_CFG6_ENA_FBCLKC2                       BIT(6)
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x)                    ((x) & GENMASK(5, 0))
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M                     GENMASK(5, 0)

#define HSIO_PLL5G_STATUS0_RANGE_LIM                      BIT(12)
#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR               BIT(11)
#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR                BIT(10)
#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE               BIT(9)
#define HSIO_PLL5G_STATUS0_READBACK_DATA(x)               (((x) << 1) & GENMASK(8, 1))
#define HSIO_PLL5G_STATUS0_READBACK_DATA_M                GENMASK(8, 1)
#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x)             (((x) & GENMASK(8, 1)) >> 1)
#define HSIO_PLL5G_STATUS0_LOCK_STATUS                    BIT(0)

#define HSIO_PLL5G_STATUS1_SIG_DEL(x)                     (((x) << 21) & GENMASK(28, 21))
#define HSIO_PLL5G_STATUS1_SIG_DEL_M                      GENMASK(28, 21)
#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x)                   (((x) & GENMASK(28, 21)) >> 21)
#define HSIO_PLL5G_STATUS1_GAIN_STAT(x)                   (((x) << 16) & GENMASK(20, 16))
#define HSIO_PLL5G_STATUS1_GAIN_STAT_M                    GENMASK(20, 16)
#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x)                 (((x) & GENMASK(20, 16)) >> 16)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x)                   (((x) << 4) & GENMASK(13, 4))
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M                    GENMASK(13, 4)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x)                 (((x) & GENMASK(13, 4)) >> 4)
#define HSIO_PLL5G_STATUS1_FSM_STAT(x)                    (((x) << 1) & GENMASK(3, 1))
#define HSIO_PLL5G_STATUS1_FSM_STAT_M                     GENMASK(3, 1)
#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x)                  (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_PLL5G_STATUS1_FSM_LOCK                       BIT(0)

#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST              BIT(31)
#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE               BIT(30)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x)          (((x) << 20) & GENMASK(23, 20))
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M           GENMASK(23, 20)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x)        (((x) & GENMASK(23, 20)) >> 20)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x)          (((x) << 16) & GENMASK(19, 16))
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M           GENMASK(19, 16)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x)        (((x) & GENMASK(19, 16)) >> 16)
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x)       ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M        GENMASK(15, 0)

#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x)            (((x) << 4) & GENMASK(7, 4))
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M             GENMASK(7, 4)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x)          (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY                   BIT(2)
#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N                 BIT(1)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL                   BIT(0)

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x)             (((x) << 16) & GENMASK(31, 16))
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M              GENMASK(31, 16)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x)           (((x) & GENMASK(31, 16)) >> 16)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x)        ((x) & GENMASK(15, 0))
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M         GENMASK(15, 0)

#define HSIO_RCOMP_CFG0_PWD_ENA                           BIT(13)
#define HSIO_RCOMP_CFG0_RUN_CAL                           BIT(12)
#define HSIO_RCOMP_CFG0_SPEED_SEL(x)                      (((x) << 10) & GENMASK(11, 10))
#define HSIO_RCOMP_CFG0_SPEED_SEL_M                       GENMASK(11, 10)
#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x)                    (((x) & GENMASK(11, 10)) >> 10)
#define HSIO_RCOMP_CFG0_MODE_SEL(x)                       (((x) << 8) & GENMASK(9, 8))
#define HSIO_RCOMP_CFG0_MODE_SEL_M                        GENMASK(9, 8)
#define HSIO_RCOMP_CFG0_MODE_SEL_X(x)                     (((x) & GENMASK(9, 8)) >> 8)
#define HSIO_RCOMP_CFG0_FORCE_ENA                         BIT(4)
#define HSIO_RCOMP_CFG0_RCOMP_VAL(x)                      ((x) & GENMASK(3, 0))
#define HSIO_RCOMP_CFG0_RCOMP_VAL_M                       GENMASK(3, 0)

#define HSIO_RCOMP_STATUS_BUSY                            BIT(12)
#define HSIO_RCOMP_STATUS_DELTA_ALERT                     BIT(7)
#define HSIO_RCOMP_STATUS_RCOMP(x)                        ((x) & GENMASK(3, 0))
#define HSIO_RCOMP_STATUS_RCOMP_M                         GENMASK(3, 0)

#define HSIO_SYNC_ETH_CFG_RSZ                             0x4

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x)             (((x) << 4) & GENMASK(7, 4))
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M              GENMASK(7, 4)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x)           (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x)             (((x) << 1) & GENMASK(3, 1))
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M              GENMASK(3, 1)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x)           (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA                    BIT(0)

#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA        BIT(0)

#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x)                  (((x) << 13) & GENMASK(16, 13))
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M                   GENMASK(16, 13)
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x)                (((x) & GENMASK(16, 13)) >> 13)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x)                  (((x) << 11) & GENMASK(12, 11))
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M                   GENMASK(12, 11)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x)                (((x) & GENMASK(12, 11)) >> 11)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x)                 (((x) << 8) & GENMASK(10, 8))
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M                  GENMASK(10, 8)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x)               (((x) & GENMASK(10, 8)) >> 8)
#define HSIO_S1G_DES_CFG_DES_BW_ANA(x)                    (((x) << 5) & GENMASK(7, 5))
#define HSIO_S1G_DES_CFG_DES_BW_ANA_M                     GENMASK(7, 5)
#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x)                  (((x) & GENMASK(7, 5)) >> 5)
#define HSIO_S1G_DES_CFG_DES_SWAP_ANA                     BIT(4)
#define HSIO_S1G_DES_CFG_DES_BW_HYST(x)                   (((x) << 1) & GENMASK(3, 1))
#define HSIO_S1G_DES_CFG_DES_BW_HYST_M                    GENMASK(3, 1)
#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x)                 (((x) & GENMASK(3, 1)) >> 1)
#define HSIO_S1G_DES_CFG_DES_SWAP_HYST                    BIT(0)

#define HSIO_S1G_IB_CFG_IB_FX100_ENA                      BIT(27)
#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x)                    (((x) << 24) & GENMASK(26, 24))
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M                     GENMASK(26, 24)
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x)                  (((x) & GENMASK(26, 24)) >> 24)
#define HSIO_S1G_IB_CFG_IB_DET_LEV(x)                     (((x) << 19) & GENMASK(21, 19))
#define HSIO_S1G_IB_CFG_IB_DET_LEV_M                      GENMASK(21, 19)
#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x)                   (((x) & GENMASK(21, 19)) >> 19)
#define HSIO_S1G_IB_CFG_IB_HYST_LEV                       BIT(14)
#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM                   BIT(13)
#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING                BIT(12)
#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV                     BIT(11)
#define HSIO_S1G_IB_CFG_IB_ENA_HYST                       BIT(10)
#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP                BIT(9)
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x)                     (((x) << 6) & GENMASK(8, 6))
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M                      GENMASK(8, 6)
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x)                   (((x) & GENMASK(8, 6)) >> 6)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x)             (((x) << 4) & GENMASK(5, 4))
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M              GENMASK(5, 4)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x)           (((x) & GENMASK(5, 4)) >> 4)
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x)               ((x) & GENMASK(3, 0))
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M                GENMASK(3, 0)

#define HSIO_S1G_OB_CFG_OB_SLP(x)                         (((x) << 17) & GENMASK(18, 17))
#define HSIO_S1G_OB_CFG_OB_SLP_M                          GENMASK(18, 17)
#define HSIO_S1G_OB_CFG_OB_SLP_X(x)                       (((x) & GENMASK(18, 17)) >> 17)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x)                    (((x) << 13) & GENMASK(16, 13))
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M                     GENMASK(16, 13)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x)                  (((x) & GENMASK(16, 13)) >> 13)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x)               (((x) << 10) & GENMASK(12, 10))
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M                GENMASK(12, 10)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x)             (((x) & GENMASK(12, 10)) >> 10)
#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL                   BIT(9)
#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG                   BIT(8)
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x)                    (((x) << 4) & GENMASK(7, 4))
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M                     GENMASK(7, 4)
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x)                  (((x) & GENMASK(7, 4)) >> 4)
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x)               ((x) & GENMASK(3, 0))
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M                GENMASK(3, 0)

#define HSIO_S1G_SER_CFG_SER_IDLE                         BIT(9)
#define HSIO_S1G_SER_CFG_SER_DEEMPH                       BIT(8)
#define HSIO_S1G_SER_CFG_SER_CPMD_SEL                     BIT(7)
#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD                    BIT(6)
#define HSIO_S1G_SER_CFG_SER_ALISEL(x)                    (((x) << 4) & GENMASK(5, 4))
#define HSIO_S1G_SER_CFG_SER_ALISEL_M                     GENMASK(5, 4)
#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
#define HSIO_S1G_SER_CFG_SER_ENHYS                        BIT(3)
#define HSIO_S1G_SER_CFG_SER_BIG_WIN                      BIT(2)
#define HSIO_S1G_SER_CFG_SER_EN_WIN                       BIT(1)
#define HSIO_S1G_SER_CFG_SER_ENALI                        BIT(0)

#define HSIO_S1G_COMMON_CFG_SYS_RST                       BIT(31)
#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA           BIT(21)
#define HSIO_S1G_COMMON_CFG_ENA_LANE                      BIT(18)
#define HSIO_S1G_COMMON_CFG_PWD_RX                        BIT(17)
#define HSIO_S1G_COMMON_CFG_PWD_TX                        BIT(16)
#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x)                  (((x) << 13) & GENMASK(15, 13))
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M                   GENMASK(15, 13)
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x)                (((x) & GENMASK(15, 13)) >> 13)
#define HSIO_S1G_COMMON_CFG_ENA_DIRECT                    BIT(12)
#define HSIO_S1G_COMMON_CFG_ENA_ELOOP                     BIT(11)
#define HSIO_S1G_COMMON_CFG_ENA_FLOOP                     BIT(10)
#define HSIO_S1G_COMMON_CFG_ENA_ILOOP                     BIT(9)
#define HSIO_S1G_COMMON_CFG_ENA_PLOOP                     BIT(8)
#define HSIO_S1G_COMMON_CFG_HRATE                         BIT(7)
#define HSIO_S1G_COMMON_CFG_IF_MODE                       BIT(0)

#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2                  BIT(22)
#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2                  BIT(21)
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x)             (((x) << 8) & GENMASK(15, 8))
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M              GENMASK(15, 8)
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x)           (((x) & GENMASK(15, 8)) >> 8)
#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA                      BIT(7)
#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA            BIT(6)
#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA            BIT(5)
#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL                  BIT(3)

#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE              BIT(12)
#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR                   BIT(11)
#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR          BIT(10)
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x)                ((x) & GENMASK(7, 0))
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M                 GENMASK(7, 0)

#define HSIO_S1G_DFT_CFG0_LAZYBIT                         BIT(31)
#define HSIO_S1G_DFT_CFG0_INV_DIS                         BIT(23)
#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x)                     (((x) << 20) & GENMASK(21, 20))
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M                      GENMASK(21, 20)
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x)                   (((x) & GENMASK(21, 20)) >> 20)
#define HSIO_S1G_DFT_CFG0_TEST_MODE(x)                    (((x) << 16) & GENMASK(18, 16))
#define HSIO_S1G_DFT_CFG0_TEST_MODE_M                     GENMASK(18, 16)
#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x)                  (((x) & GENMASK(18, 16)) >> 16)
#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS                 BIT(4)
#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA                   BIT(3)
#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA                      BIT(2)
#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA                      BIT(0)

#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x)               (((x) << 8) & GENMASK(17, 8))
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M                GENMASK(17, 8)
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x)             (((x) & GENMASK(17, 8)) >> 8)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x)                 (((x) << 4) & GENMASK(7, 4))
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M                  GENMASK(7, 4)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x)               (((x) & GENMASK(7, 4)) >>