path: root/drivers/net/ethernet/via/via-velocity.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * File: via-velocity.h
 *
 * Purpose: Header file to define driver's private structures.
 *
 * Author: Chuang Liang-Shing, AJ Jiang
 *
 * Date: Jan 24, 2003
 */


#ifndef VELOCITY_H
#define VELOCITY_H

#define VELOCITY_TX_CSUM_SUPPORT

#define VELOCITY_NAME          "via-velocity"
#define VELOCITY_FULL_DRV_NAM  "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
#define VELOCITY_VERSION       "1.15"

#define VELOCITY_IO_SIZE	256

#define PKT_BUF_SZ          1540

#define MAX_UNITS           8
#define OPTION_DEFAULT      { [0 ... MAX_UNITS-1] = -1}

#define REV_ID_VT6110       (0)

#define BYTE_REG_BITS_ON(x,p)       do { writeb(readb((p))|(x),(p));} while (0)
#define WORD_REG_BITS_ON(x,p)       do { writew(readw((p))|(x),(p));} while (0)
#define DWORD_REG_BITS_ON(x,p)      do { writel(readl((p))|(x),(p));} while (0)

#define BYTE_REG_BITS_IS_ON(x,p)    (readb((p)) & (x))
#define WORD_REG_BITS_IS_ON(x,p)    (readw((p)) & (x))
#define DWORD_REG_BITS_IS_ON(x,p)   (readl((p)) & (x))

#define BYTE_REG_BITS_OFF(x,p)      do { writeb(readb((p)) & (~(x)),(p));} while (0)
#define WORD_REG_BITS_OFF(x,p)      do { writew(readw((p)) & (~(x)),(p));} while (0)
#define DWORD_REG_BITS_OFF(x,p)     do { writel(readl((p)) & (~(x)),(p));} while (0)

#define BYTE_REG_BITS_SET(x,m,p)    do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
#define WORD_REG_BITS_SET(x,m,p)    do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
#define DWORD_REG_BITS_SET(x,m,p)   do { writel( (readl((p)) & (~(m)))|(x),(p));}  while (0)

#define VAR_USED(p)     do {(p)=(p);} while (0)

/*
 * Purpose: Structures for MAX RX/TX descriptors.
 */


#define B_OWNED_BY_CHIP     1
#define B_OWNED_BY_HOST     0

/*
 * Bits in the RSR0 register
 */

#define RSR_DETAG	cpu_to_le16(0x0080)
#define RSR_SNTAG	cpu_to_le16(0x0040)
#define RSR_RXER	cpu_to_le16(0x0020)
#define RSR_RL		cpu_to_le16(0x0010)
#define RSR_CE		cpu_to_le16(0x0008)
#define RSR_FAE		cpu_to_le16(0x0004)
#define RSR_CRC		cpu_to_le16(0x0002)
#define RSR_VIDM	cpu_to_le16(0x0001)

/*
 * Bits in the RSR1 register
 */

#define RSR_RXOK	cpu_to_le16(0x8000) // rx OK
#define RSR_PFT		cpu_to_le16(0x4000) // Perfect filtering address match
#define RSR_MAR		cpu_to_le16(0x2000) // MAC accept multicast address packet
#define RSR_BAR		cpu_to_le16(0x1000) // MAC accept broadcast address packet
#define RSR_PHY		cpu_to_le16(0x0800) // MAC accept physical address packet
#define RSR_VTAG	cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
#define RSR_STP		cpu_to_le16(0x0200) // start of packet
#define RSR_EDP		cpu_to_le16(0x0100) // end of packet

/*
 * Bits in the CSM register
 */

#define CSM_IPOK            0x40	//IP Checksum validation ok
#define CSM_TUPOK           0x20	//TCP/UDP Checksum validation ok
#define CSM_FRAG            0x10	//Fragment IP datagram
#define CSM_IPKT            0x04	//Received an IP packet
#define CSM_TCPKT           0x02	//Received a TCP packet
#define CSM_UDPKT           0x01	//Received a UDP packet

/*
 * Bits in the TSR0 register
 */

#define TSR0_ABT	cpu_to_le16(0x0080) // Tx abort because of excessive collision
#define TSR0_OWT	cpu_to_le16(0x0040) // Jumbo frame Tx abort
#define TSR0_OWC	cpu_to_le16(0x0020) // Out of window collision
#define TSR0_COLS	cpu_to_le16(0x0010) // experience collision in this transmit event
#define TSR0_NCR3	cpu_to_le16(0x0008) // collision retry counter[3]
#define TSR0_NCR2	cpu_to_le16(0x0004) // collision retry counter[2]
#define TSR0_NCR1	cpu_to_le16(0x0002) // collision retry counter[1]
#define TSR0_NCR0	cpu_to_le16(0x0001) // collision retry counter[0]
#define TSR0_TERR	cpu_to_le16(0x8000) //
#define TSR0_FDX	cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
#define TSR0_GMII	cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
#define TSR0_LNKFL	cpu_to_le16(0x1000) // packet serviced during link down
#define TSR0_SHDN	cpu_to_le16(0x0400) // shutdown case
#define TSR0_CRS	cpu_to_le16(0x0200) // carrier sense lost
#define TSR0_CDH	cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)

//
// Bits in the TCR0 register
//
#define TCR0_TIC            0x80	// assert interrupt immediately while descriptor has been send complete
#define TCR0_PIC            0x40	// priority interrupt request, INA# is issued over adaptive interrupt scheme
#define TCR0_VETAG          0x20	// enable VLAN tag
#define TCR0_IPCK           0x10	// request IP  checksum calculation.
#define TCR0_UDPCK          0x08	// request UDP checksum calculation.
#define TCR0_TCPCK          0x04	// request TCP checksum calculation.
#define TCR0_JMBO           0x02	// indicate a jumbo packet in GMAC side
#define TCR0_CRC            0x01	// disable CRC generation

#define TCPLS_NORMAL        3
#define TCPLS_START         2
#define TCPLS_END           1
#define TCPLS_MED           0


// max transmit or receive buffer size
#define CB_RX_BUF_SIZE     2048UL	// max buffer size
					// NOTE: must be multiple of 4

#define CB_MAX_RD_NUM       512	// MAX # of RD
#define CB_MAX_TD_NUM       256	// MAX # of TD

#define CB_INIT_RD_NUM_3119 128	// init # of RD, for setup VT3119
#define CB_INIT_TD_NUM_3119 64	// init # of TD, for setup VT3119

#define CB_INIT_RD_NUM      128	// init # of RD, for setup default
#define CB_INIT_TD_NUM      64	// init # of TD, for setup default

// for 3119
#define CB_TD_RING_NUM      4	// # of TD rings.
#define CB_MAX_SEG_PER_PKT  7	// max data seg per packet (Tx)


/*
 *	If collisions excess 15 times , tx will abort, and
 *	if tx fifo underflow, tx will fail
 *	we should try to resend it
 */

#define CB_MAX_TX_ABORT_RETRY   3

/*
 *	Receive descriptor
 */

struct rdesc0 {
	__le16 RSR;		/* Receive status */
	__le16 len;		/* bits 0--13; bit 15 - owner */
};

struct rdesc1 {
	__le16 PQTAG;
	u8 CSM;
	u8 IPKT;
};

enum {
	RX_INTEN = cpu_to_le16(0x8000)
};

struct rx_desc {
	struct rdesc0 rdesc0;
	struct rdesc1 rdesc1;
	__le32 pa_low;		/* Low 32 bit PCI address */
	__le16 pa_high;		/* Next 16 bit PCI address (48 total) */
	__le16 size;		/* bits 0--14 - frame size, bit 15 - enable int. */
} __packed;

/*
 *	Transmit descriptor
 */

struct tdesc0 {
	__le16 TSR;		/* Transmit status register */
	__le16 len;		/* bits 0--13 - size of frame, bit 15 - owner */
};

struct tdesc1 {
	__le16 vlan;
	u8 TCR;
	u8 cmd;			/* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
} __packed;

enum {
	TD_QUEUE = cpu_to_le16(0x8000)
};

struct td_buf {
	__le32 pa_low;
	__le16 pa_high;
	__le16 size;		/* bits 0--13 - size, bit 15 - queue */
} __packed;

struct tx_desc {
	struct tdesc0 tdesc0;
	struct tdesc1 tdesc1;
	struct td_buf td_buf[7];
};

struct velocity_rd_info {
	struct sk_buff *skb;
	dma_addr_t skb_dma;
};

/*
 *	Used to track transmit side buffers.
 */

struct velocity_td_info {
	struct sk_buff *skb;
	int nskb_dma;
	dma_addr_t skb_dma[7];
};

enum  velocity_owner {
	OWNED_BY_HOST = 0,
	OWNED_BY_NIC = cpu_to_le16(0x8000)
};


/*
 *	MAC registers and macros.
 */


#define MCAM_SIZE           64
#define VCAM_SIZE           64
#define TX_QUEUE_NO         4

#define MAX_HW_MIB_COUNTER  32
#define VELOCITY_MIN_MTU    (64)
#define VELOCITY_MAX_MTU    (9000)