path: root/drivers/net/phy/mediatek/mtk-ge-soc.c

// SPDX-License-Identifier: GPL-2.0+
#include <linux/bitfield.h>
#include <linux/bitmap.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/pinctrl/consumer.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/of.h>

#include "../phylib.h"
#include "mtk.h"

#define MTK_PHY_MAX_LEDS			2

#define MTK_GPHY_ID_MT7981			0x03a29461
#define MTK_GPHY_ID_MT7988			0x03a29481
#define MTK_GPHY_ID_AN7581			0x03a294c1
#define MTK_GPHY_ID_AN7583			0xc0ff0420

#define MTK_EXT_PAGE_ACCESS			0x1f
#define MTK_PHY_PAGE_STANDARD			0x0000
#define MTK_PHY_PAGE_EXTENDED_3			0x0003

#define MTK_PHY_LPI_REG_14			0x14
#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)

#define MTK_PHY_LPI_REG_1c			0x1c
#define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)

#define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30

/* Registers on Token Ring debug nodes */
/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
/* NormMseLoThresh */
#define NORMAL_MSE_LO_THRESH_MASK		GENMASK(15, 8)

/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
/* RemAckCntLimitCtrl */
#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK	GENMASK(2, 1)

/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
/* VcoSlicerThreshBitsHigh */
#define VCO_SLICER_THRESH_HIGH_MASK		GENMASK(23, 0)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
/* DfeTailEnableVgaThresh1000 */
#define DFE_TAIL_EANBLE_VGA_TRHESH_1000		GENMASK(5, 1)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
/* MrvlTrFix100Kp */
#define MRVL_TR_FIX_100KP_MASK			GENMASK(22, 20)
/* MrvlTrFix100Kf */
#define MRVL_TR_FIX_100KF_MASK			GENMASK(19, 17)
/* MrvlTrFix1000Kp */
#define MRVL_TR_FIX_1000KP_MASK			GENMASK(16, 14)
/* MrvlTrFix1000Kf */
#define MRVL_TR_FIX_1000KF_MASK			GENMASK(13, 11)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
/* VgaDecRate */
#define VGA_DECIMATION_RATE_MASK		GENMASK(8, 5)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
/* SlvDSPreadyTime */
#define SLAVE_DSP_READY_TIME_MASK		GENMASK(22, 15)
/* MasDSPreadyTime */
#define MASTER_DSP_READY_TIME_MASK		GENMASK(14, 7)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
/* EnabRandUpdTrig */
#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER	BIT(8)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
/* ResetSyncOffset */
#define RESET_SYNC_OFFSET_MASK			GENMASK(11, 8)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
/* FfeUpdGainForceVal */
#define FFE_UPDATE_GAIN_FORCE_VAL_MASK		GENMASK(9, 7)
/* FfeUpdGainForce */
#define FFE_UPDATE_GAIN_FORCE			BIT(6)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
/* TrFreeze */
#define TR_FREEZE_MASK				GENMASK(11, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
/* SS: Steady-state, KP: Proportional Gain */
/* SSTrKp100 */
#define SS_TR_KP100_MASK			GENMASK(21, 19)
/* SSTrKf100 */
#define SS_TR_KF100_MASK			GENMASK(18, 16)
/* SSTrKp1000Mas */
#define SS_TR_KP1000_MASTER_MASK		GENMASK(15, 13)
/* SSTrKf1000Mas */
#define SS_TR_KF1000_MASTER_MASK		GENMASK(12, 10)
/* SSTrKp1000Slv */
#define SS_TR_KP1000_SLAVE_MASK			GENMASK(9, 7)
/* SSTrKf1000Slv */
#define SS_TR_KF1000_SLAVE_MASK			GENMASK(6, 4)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
/* clear this bit if wanna select from AFE */
/* Regsigdet_sel_1000 */
#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE	BIT(4)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
/* RegEEE_st2TrKf1000 */
#define EEE1000_STAGE2_TR_KF_MASK		GENMASK(13, 11)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
/* RegEEE_slv_waketr_timer_tar */
#define SLAVE_WAKETR_TIMER_MASK			GENMASK(20, 11)
/* RegEEE_slv_remtx_timer_tar */
#define SLAVE_REMTX_TIMER_MASK			GENMASK(10, 1)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
/* RegEEE_slv_wake_int_timer_tar */
#define SLAVE_WAKEINT_TIMER_MASK		GENMASK(10, 1)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
/* RegEEE_trfreeze_timer2 */
#define TR_FREEZE_TIMER2_MASK			GENMASK(9, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
/* RegEEE100Stg1_tar */
#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK	GENMASK(8, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN	BIT(11)

#define ANALOG_INTERNAL_OPERATION_MAX_US	20
#define TXRESERVE_MIN				0
#define TXRESERVE_MAX				7

#define MTK_PHY_ANARG_RG			0x10
#define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)

/* Registers on MDIO_MMD_VEND1 */
#define MTK_PHY_TXVLD_DA_RG			0x12
#define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
#define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
#define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
#define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
#define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
#define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
#define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
#define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
#define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)

#define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
#define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
#define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)

#define MTK_PHY_RXADC_CTRL_RG7			0xc6
#define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)

#define MTK_PHY_RXADC_CTRL_RG9			0xc8
#define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
#define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
#define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
#define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)

#define MTK_PHY_LDO_OUTPUT_V			0xd7

#define MTK_PHY_RG_ANA_CAL_RG0			0xdb
#define   MTK_PHY_RG_CAL_CKINV			BIT(12)
#define   MTK_PHY_RG_ANA_CALEN			BIT(8)
#define   MTK_PHY_RG_ZCALEN_A			BIT(0)

#define MTK_PHY_RG_ANA_CAL_RG1			0xdc
#define   MTK_PHY_RG_ZCALEN_B			BIT(12)
#define   MTK_PHY_RG_ZCALEN_C			BIT(8)
#define   MTK_PHY_RG_ZCALEN_D			BIT(4)
#define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)

#define MTK_PHY_RG_ANA_CAL_RG5			0xe0
#define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)

#define MTK_PHY_RG_TX_FILTER			0xfe

#define MTK_