path: root/drivers/net/ucc_geth.h

/*
 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
 *
 * Author: Shlomi Gridish <gridish@freescale.com>
 *
 * Description:
 * Internal header file for UCC Gigabit Ethernet unit routines.
 *
 * Changelog:
 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
 * - Rearrange code and style fixes
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#ifndef __UCC_GETH_H__
#define __UCC_GETH_H__

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/fsl_devices.h>

#include <asm/immap_qe.h>
#include <asm/qe.h>

#include <asm/ucc.h>
#include <asm/ucc_fast.h>

#include "ucc_geth_mii.h"

#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
#define DRV_NAME "ucc_geth"
#define DRV_VERSION "1.1"

#define NUM_TX_QUEUES                   8
#define NUM_RX_QUEUES                   8
#define NUM_BDS_IN_PREFETCHED_BDS       4
#define TX_IP_OFFSET_ENTRY_MAX          8
#define NUM_OF_PADDRS                   4
#define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
#define ENET_INIT_PARAM_MAX_ENTRIES_TX  8

struct ucc_geth {
	struct ucc_fast uccf;
	u8 res0[0x100 - sizeof(struct ucc_fast)];

	u32 maccfg1;		/* mac configuration reg. 1 */
	u32 maccfg2;		/* mac configuration reg. 2 */
	u32 ipgifg;		/* interframe gap reg.  */
	u32 hafdup;		/* half-duplex reg.  */
	u8 res1[0x10];
	u8 miimng[0x18];	/* MII management structure moved to _mii.h */
	u32 ifctl;		/* interface control reg */
	u32 ifstat;		/* interface statux reg */
	u32 macstnaddr1;	/* mac station address part 1 reg */
	u32 macstnaddr2;	/* mac station address part 2 reg */
	u8 res2[0x8];
	u32 uempr;		/* UCC Ethernet Mac parameter reg */
	u32 utbipar;		/* UCC tbi address reg */
	u16 uescr;		/* UCC Ethernet statistics control reg */
	u8 res3[0x180 - 0x15A];
	u32 tx64;		/* Total number of frames (including bad
				   frames) transmitted that were exactly of the
				   minimal length (64 for un tagged, 68 for
				   tagged, or with length exactly equal to the
				   parameter MINLength */
	u32 tx127;		/* Total number of frames (including bad
				   frames) transmitted that were between
				   MINLength (Including FCS length==4) and 127
				   octets */
	u32 tx255;		/* Total number of frames (including bad
				   frames) transmitted that were between 128
				   (Including FCS length==4) and 255 octets */
	u32 rx64;		/* Total number of frames received including
				   bad frames that were exactly of the mninimal
				   length (64 bytes) */
	u32 rx127;		/* Total number of frames (including bad
				   frames) received that were between MINLength
				   (Including FCS length==4) and 127 octets */
	u32 rx255;		/* Total number of frames (including bad
				   frames) received that were between 128
				   (Including FCS length==4) and 255 octets */
	u32 txok;		/* Total number of octets residing in frames
				   that where involved in succesfull
				   transmission */
	u16 txcf;		/* Total number of PAUSE control frames
				   transmitted by this MAC */
	u8 res4[0x2];
	u32 tmca;		/* Total number of frames that were transmitted
				   succesfully with the group address bit set
				   that are not broadcast frames */
	u32 tbca;		/* Total number of frames transmitted
				   succesfully that had destination address
				   field equal to the broadcast address */
	u32 rxfok;		/* Total number of frames received OK */
	u32 rxbok;		/* Total number of octets received OK */
	u32 rbyt;		/* Total number of octets received including
				   octets in bad frames. Must be implemented in
				   HW because it includes octets in frames that
				   never even reach the UCC */
	u32 rmca;		/* Total number of frames that were received
				   succesfully with the group address bit set
				   that are not broadcast frames */
	u32 rbca;		/* Total number of frames received succesfully
				   that had destination address equal to the
				   broadcast address */
	u32 scar;		/* Statistics carry register */
	u32 scam;		/* Statistics caryy mask register */
	u8 res5[0x200 - 0x1c4];
} __attribute__ ((packed));

/* UCC GETH TEMODR Register */
#define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100	/* enable Tx statistics
							 */
#define TEMODER_SCHEDULER_ENABLE                0x2000	/* enable scheduler */
#define TEMODER_IP_CHECKSUM_GENERATE            0x0400	/* generate IPv4
							   checksums */
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200	/* enable performance
							   optimization
							   enhancement (mode1) */
#define TEMODER_RMON_STATISTICS                 0x0100	/* enable tx statistics
							 */
#define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15)	/* Number of queues <<
							   shift */

/* UCC GETH TEMODR Register */
#define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000	/* enable Rx
								   statistics */
#define REMODER_RX_EXTENDED_FEATURES            0x80000000	/* enable
								   extended
								   features */
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 )	/* vlan operation
							   tagged << shift */
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)	/* vlan operation non
							   tagged << shift */
#define REMODER_RX_QOS_MODE_SHIFT               (31-15)	/* rx QoS mode << shift
							 */
#define REMODER_RMON_STATISTICS                 0x00001000	/* enable rx
								   statistics */
#define REMODER_RX_EXTENDED_FILTERING           0x00000800	/* extended
								   filtering
								   vs.
								   mpc82xx-like
								   filtering */
#define REMODER_NUM_OF_QUEUES_SHIFT             (31-23)	/* Number of queues <<
							   shift */
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008	/* enable
								   dynamic max
								   frame length
								 */
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004	/* enable
								   dynamic min
								   frame length
								 */
#define REMODER_IP_CHECKSUM_CHECK               0x00000002	/* check IPv4
								   checksums */
#define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001	/* align ip
								   address to
								   4-byte
								   boundary */

/* UCC GETH Event Register */
#define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
		    UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
		    UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
		    UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)

#define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
		    UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
		    UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
		    UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)

#define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
		    UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
		    UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
		    UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)

#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
		    UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
		    UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)

#define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
#define UCCE_TX_EVENTS	(UCCE_TXB | UCC_GETH_UCCE_TXE)

/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
#define MACCFG1_FLOW_RX                         0x00000020	/* Flow Control
								   Rx */
#define MACCFG1_FLOW_TX                         0x00000010	/* Flow Control
								   Tx */
#define MACCFG1_ENABLE_SYNCHED_RX               0x00000008	/* Rx Enable
								   synchronized
								   to Rx stream
								 */
#define MACCFG1_ENABLE_RX                       0x00000004	/* Enable Rx */
#define MACCFG1_ENABLE_SYNCHED_TX               0x00000002	/* Tx Enable
								   synchronized
								   to Tx stream
								 */
#define MACCFG1_ENABLE_TX                       0x00000001	/* Enable Tx */

/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
#define MACCFG2_PREL_SHIFT                      (31 - 19)	/* Preamble
								   Length <<
								   shift */
#define MACCFG2_PREL_MASK                       0x0000f000	/* Preamble
								   Length mask */
#define MACCFG2_SRP                             0x00000080	/* Soft Receive
								   Preamble */
#define MACCFG2_STP                             0x00000040	/* Soft
								   Transmit
								   Preamble */
#define MACCFG2_RESERVED_1                      0x00000020	/* Reserved -
								   must be set
								   to 1 */
#define MACCFG2_LC                              0x00000010	/* Length Check
								 */
#define MACCFG2_MPE                             0x00000008	/* Magic packet
								   detect */
#define MACCFG2_FDX                             0x00000001	/* Full Duplex */
#define MACCFG2_FDX_MASK                        0x00000001	/* Full Duplex
								   mask */
#define MACCFG2_PAD_CRC                         0x00000004
#define MACCFG2_CRC_EN                          0x00000002
#define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000	/* Neither
								   Padding
								   short frames
								   nor CRC */
#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002	/* Append CRC
								   only */
#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
#define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100	/* nibble mode
								   (MII/RMII/RGMII
								   10/100bps) */
#define MACCFG2_INTERFACE_MODE_BYTE             0x00000200	/* byte mode
								   (GMII/TBI/RTB/RGMII
								   1000bps ) */
#define MACCFG2_INTERFACE_MODE_MASK             0x00000300	/* mask
								   covering all
								   relevant
								   bits */

/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)	/* Non
								   back-to-back
								   inter frame
								   gap part 1.
								   << shift */
#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)	/* Non
								   back-to-back
								   inter frame
								   gap part 2.
								   << shift */
#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)	/* Mimimum IFG
								   Enforcement
								   << shift */
#define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)	/* back-to-back
								   inter frame
								   gap << shift
								 */
#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127	/* Non back-to-back
							   inter frame gap part
							   1. max val */
#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127	/* Non back-to-back
							   inter frame gap part
							   2. max val */
#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255	/* Mimimum IFG
							   Enforcement max val */
#define IPGIFG_BACK_TO_BACK_IFG_MAX             127	/* back-to-back inter
							   frame gap max val */
#define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
#define IPGIFG_NBTB_IPG_MASK                    0x007F0000
#define IPGIFG_MIN_IFG_MASK                     0x0000FF00
#define IPGIFG_BTB_IPG_MASK                     0x0000007F

/* UCC GETH HAFDUP (Half Duplex Register) */
#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)	/* Alternate
								   Binary
								   Exponential
								   Backoff
								   Truncation
								   << shift */
#define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf	/* Alternate Binary
							   Exponential Backoff
							   Truncation max val */
#define HALFDUP_ALT_BEB                         0x00080000	/* Alternate
								   Binary
								   Exponential
								   Backoff */
#define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000	/* Back
								   pressure no
								   backoff */
#define HALFDUP_NO_BACKOFF                      0x00020000	/* No Backoff */
#define HALFDUP_EXCESSIVE_DEFER                 0x00010000	/* Excessive
								   Defer */
#define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)	/* Maximum
								   Retransmission
								   << shift */
#define HALFDUP_MAX_RETRANSMISSION_MAX          0xf	/* Maximum
							   Retransmission max
							   val */
#define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)	/* Collision
								   Window <<
								   shift */
#define HALFDUP_COLLISION_WINDOW_MAX            0x3f	/* Collision Window max
							   val */
#define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
#define HALFDUP_RETRANS_MASK                    0x0000F000
#define HALFDUP_COL_WINDOW_MASK                 0x0000003F

/* UCC GETH UCCS (Ethernet Status Register) */
#define UCCS_BPR                                0x02	/* Back pressure (in
							   half duplex mode) */
#define UCCS_PAU                                0x02	/* Pause state (in full
							   duplex mode) */
#define UCCS_MPD                                0x01	/* Magic Packet
							   Detected */

/* UCC GETH IFSTAT (Interface Status Register) */
#define IFSTAT_EXCESS_DEFER                     0x00000200	/* Excessive
								   transmission
								   defer */

/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
#define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)	/* Station
								   address 6th
								   octet <<
								   shift */
#define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)	/* Station
								   address 5th
								   octet <<
								   shift */
#define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)	/* Station
								   address 4th
								   octet <<
								   shift */
#define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)	/* Station
								   address 3rd
								   octet <<
								   shift */

/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
#define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)	/* Station
								   address 2nd
								   octet <<
								   shift */
#define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)	/* Station
								   address 1st
								   octet <<
								   shift */

/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
#define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)	/* Pause time
								   value <<
								   shift */
#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)	/* Extended
								   pause time
								   value <<
								   shift */

/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
#define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)	/* Phy address
								   << shift */
#define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f	/* Phy address
								   mask */

/* UCC GETH UESCR (Ethernet Statistics Control Register) */
#define UESCR_AUTOZ                             0x8000	/* Automatically zero
							   addressed
							   statistical counter
							   values */
#define UESCR_CLRCNT                            0x4000	/* Clear all statistics
							   counters */
#define UESCR_MAXCOV_SHIFT                      (15 -  7)	/* Max
								   Coalescing
								   Value <<
								   shift */
#define UESCR_SCOV_SHIFT                        (15 - 15)	/* Status
								   Coalescing
								   Value <<
								   shift */

/* UCC GETH UDSR (Data Synchronization Register) */
#define UDSR_MAGIC                              0x067E

struct ucc_geth_thread_data_tx {
	u8 res0[104];
} __attribute__ ((packed));

struct ucc_geth_thread_data_rx {
	u8 res0[40];
} __attribute__ ((packed));

/* Send Queue Queue-Descriptor */
struct ucc_geth_send_queue_qd {
	u32 bd_ring_base;	/* pointer to BD ring base address */
	u8 res0[0x8];
	u32 last_bd_completed_address;/* initialize to last entry in BD ring */
	u8 res1[0x30];
} __attribute__ ((packed));

struct ucc_geth_send_queue_mem_region {
	struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
} __attribute__ ((packed));

struct ucc_geth_thread_tx_pram {
	u8 res0[64];
} __attribute__ ((packed));

struct ucc_geth_thread_rx_pram {
	u8 res0[128];
} __attribute__ ((packed));

#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96

struct ucc_geth_scheduler {
	u16 cpucount0;		/* CPU packet counter */
	u16 cpucount1;		/* CPU packet counter */
	u16 cecount0;		/* QE packet counter */
	u16 cecount1;		/* QE packet counter */
	u16 cpucount2;		/* CPU packet counter */
	u16 cpucount3;		/* CPU packet counter */
	u16 cecount2;		/* QE packet counter */
	u16 cecount3;		/* QE packet counter */
	u16 cpucount4;		/* CPU packet counter */
	u16 cpucount5;		/* CPU packet counter */
	u16 cecount4;		/* QE packet counter */
	u16 cecount5;		/* QE packet counter */
	u16 cpucount6;		/* CPU packet counter */
	u16 cpucount7;		/* CPU packet counter */
	u16 cecount6;		/* QE packet counter */
	u16 cecount7;		/* QE packet counter */
	u32 weightstatus[NUM_TX_QUEUES];	/* accumulated weight factor */
	u32 rtsrshadow;		/* temporary variable handled by QE */
	u32 time;		/* temporary variable handled by QE */
	u32 ttl;		/* temporary variable handled by QE */
	u32 mblinterval;	/* max burst length interval */
	u16 nortsrbytetime;	/* normalized value of byte time in tsr units */
	u8 fracsiz;		/* radix 2 log value of denom. of
				   NorTSRByteTime */
	u8 res0[1];
	u8 strictpriorityq;	/* Strict Priority Mask register */
	u8 txasap;		/* Transmit ASAP register */
	u8 extrabw;		/* Extra BandWidth register */
	u8 oldwfqmask;		/* temporary variable handled by QE */
	u8 weightfactor[NUM_TX_QUEUES];
				      /**< weight factor for queues   */
	u32 minw;		/* temporary variable handled by QE */
	u8 res1[0x70 - 0x64];
} __attribute__ ((packed));

struct ucc_geth_tx_firmware_statistics_pram {
	u32 sicoltx;		/* single collision */
	u32 mulcoltx;		/* multiple collision */
	u32 latecoltxfr;	/* late collision */
	u32 frabortduecol;	/* frames aborted due to transmit collision */
	u32 frlostinmactxer;	/* frames lost due to internal MAC error
				   transmission that are not counted on any
				   other counter */
	u32 carriersenseertx;	/* carrier sense error */
	u32 frtxok;		/* frames transmitted OK */
	u32 txfrexcessivedefer;	/* frames with defferal time greater than
				   specified threshold */
	u32 txpkts256;		/* total packets (including bad) between 256
				   and 511 octets */
	u32 txpkts512;		/* total packets (including bad) between 512
				   and 1023 octets */
	u32 txpkts1024;		/* total packets (including bad) between 1024
				   and 1518 octets */
	u32 txpktsjumbo;	/* total packets (including bad) between 1024
				   and MAXLength octets */
} __attribute__ ((packed));

struct ucc_geth_rx_firmware_statistics_pram {
	u32 frrxfcser;		/* frames with crc error */
	u32 fraligner;		/* frames with alignment error */
	u32 inrangelenrxer;	/* in range length error */
	u32 outrangelenrxer;	/* out of range length error */
	u32 frtoolong;		/* frame too long */
	u32 runt;		/* runt */
	u32 verylongevent;	/* very long event */
	u32 symbolerror;	/* symbol error */
	u32 dropbsy;		/* drop because of BD not ready */
	u8 res0[0x8];
	u32 mismatchdrop;	/* drop because of MAC filtering (e.g. address
				   or type mismatch) */
	u32 underpkts;		/* total frames less than 64 octets */
	u32 pkts256;		/* total frames (including bad) between 256 and
				   511 octets */
	u32 pkts512;		/* total frames (including bad) between 512 and
				   1023 octets */
	u32 pkts1024;		/* total frames (including bad) between 1024
				   and 1518 octets */
	u32 pktsjumbo;		/* total frames (including bad) between 1024
				   and MAXLength octets */
	u32 frlossinmacer;	/* frames lost because of internal MAC error
				   that is not counted in any other counter */
	u32 pausefr;		/* pause frames */
	u8 res1[0x4];
	u32 removevlan;		/* total frames that had their VLAN tag removed
				 */
	u32 replacevlan;	/* total frames that had their VLAN tag
				   replaced */
	u32 insertvlan;		/* total frames that had their VLAN tag
				   inserted */
} __attribute__ ((packed));

struct ucc_geth_rx_interrupt_coalescing_entry {
	u32