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/*
* Linux driver for VMware's vmxnet3 ethernet NIC.
*
* Copyright (C) 2008-2024, VMware, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; version 2 of the License and no later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Maintained by: pv-drivers@vmware.com
*
*/
#ifndef _VMXNET3_DEFS_H_
#define _VMXNET3_DEFS_H_
#include "upt1_defs.h"
/* all registers are 32 bit wide */
/* BAR 1 */
enum {
VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
VMXNET3_REG_CMD = 0x20, /* Command */
VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
VMXNET3_REG_MACH = 0x30, /* MAC Address High */
VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
VMXNET3_REG_ECR = 0x40, /* Event Cause Register */
VMXNET3_REG_DCR = 0x48, /* Device capability register,
* from 0x48 to 0x80
*/
VMXNET3_REG_PTCR = 0x88, /* Passthru capbility register
* from 0x88 to 0xb0
*/
};
/* BAR 0 */
enum {
VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
};
/* For Large PT BAR, the following offset to DB register */
enum {
VMXNET3_REG_LB_TXPROD = 0x1000, /* Tx Producer Index */
VMXNET3_REG_LB_RXPROD = 0x1400, /* Rx Producer Index for ring 1 */
VMXNET3_REG_LB_RXPROD2 = 0x1800, /* Rx Producer Index for ring 2 */
};
#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
#define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */
#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
#define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */
#define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */
#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
#define VMXNET3_REG_ALIGN_MASK 0x7
/* I/O Mapped access to registers */
#define VMXNET3_IO_TYPE_PT 0
#define VMXNET3_IO_TYPE_VD 1
#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
#define VMXNET3_PMC_PSEUDO_TSC 0x10003
enum {
VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
VMXNET3_CMD_QUIESCE_DEV,
VMXNET3_CMD_RESET_DEV,
VMXNET3_CMD_UPDATE_RX_MODE,
VMXNET3_CMD_UPDATE_MAC_FILTERS,
VMXNET3_CMD_UPDATE_VLAN_FILTERS,
VMXNET3_CMD_UPDATE_RSSIDT,
VMXNET3_CMD_UPDATE_IML,
VMXNET3_CMD_UPDATE_PMCFG,
VMXNET3_CMD_UPDATE_FEATURE,
VMXNET3_CMD_RESERVED1,
VMXNET3_CMD_LOAD_PLUGIN,
VMXNET3_CMD_RESERVED2,
VMXNET3_CMD_RESERVED3,
VMXNET3_CMD_SET_COALESCE,
VMXNET3_CMD_REGISTER_MEMREGS,
VMXNET3_CMD_SET_RSS_FIELDS,
VMXNET3_CMD_RESERVED4,
VMXNET3_CMD_RESERVED5,
VMXNET3_CMD_SET_RING_BUFFER_SIZE,
VMXNET3_CMD_FIRST_GET = 0xF00D0000,
VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
VMXNET3_CMD_GET_STATS,
VMXNET3_CMD_GET_LINK,
VMXNET3_CMD_GET_PERM_MAC_LO,
VMXNET3_CMD_GET_PERM_MAC_HI,
VMXNET3_CMD_GET_DID_LO,
VMXNET3_CMD_GET_DID_HI,
VMXNET3_CMD_GET_DEV_EXTRA_INFO,
VMXNET3_CMD_GET_CONF_INTR,
VMXNET3_CMD_GET_RESERVED1,
VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
VMXNET3_CMD_GET_COALESCE,
VMXNET3_CMD_GET_RSS_FIELDS,
VMXNET3_CMD_GET_RESERVED2,
VMXNET3_CMD_GET_RESERVED3,
VMXNET3_CMD_GET_MAX_QUEUES_CONF,
VMXNET3_CMD_GET_RESERVED4,
VMXNET3_CMD_GET_MAX_CAPABILITIES,
VMXNET3_CMD_GET_DCR0_REG,
VMXNET3_CMD_GET_TSRING_DESC_SIZE,
VMXNET3_CMD_GET_DISABLED_OFFLOADS,
};
/*
* Little Endian layout of bitfields -
* Byte 0 : 7.....len.....0
* Byte 1 : oco gen 13.len.8
* Byte 2 : 5.msscof.0 ext1 dtype
* Byte 3 : 13...msscof...6
*
* Big Endian layout of bitfields -
* Byte 0: 13...msscof...6
* Byte 1 : 5.msscof.0 ext1 dtype
* Byte 2 : oco gen 13.len.8
* Byte 3 : 7.....len.....0
*
* Thus, le32_to_cpu on the dword will allow the big endian driver to read
* the bit fields correctly. And cpu_to_le32 will convert bitfields
* bit fields written by big endian driver to format required by device.
*/
struct Vmxnet3_TxDesc {
__le64 addr;
#ifdef __BIG_ENDIAN_BITFIELD
u32 msscof:14; /* MSS, checksum offset, flags */
u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
u32 dtype:1; /* descriptor type */
u32 oco:1; /* Outer csum offload */
u32 gen:1; /* generation bit */
u32 len:14;
#else
u32 len:14;
u32 gen:1; /* generation bit */
u32 oco:1; /* Outer csum offload */
u32 dtype:1; /* descriptor type */
u32 ext1:1; /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
u32 msscof:14; /* MSS, checksum offset, flags */
#endif /* __BIG_ENDIAN_BITFIELD */
#ifdef __BIG_ENDIAN_BITFIELD
u32 tci:16; /* Tag to Insert */
u32 ti:1; /* VLAN Tag Insertion */
u32 ext2:1;
u32 cq:1; /* completion request */
u32 eop:1; /* End Of Packet */
u32 om:2; /* offload mode */
u32 hlen:10; /* header len */
#else
u32 hlen:10; /* header len */
u32 om:2; /* offload mode */
u32 eop:1; /* End Of Packet */
u32 cq:1; /* completion request */
u32 ext2:1;
u32 ti:1; /* VLAN Tag Insertion */
u32 tci:16; /* Tag to Insert */
#endif /* __BIG_ENDIAN_BITFIELD */
};
/* TxDesc.OM values */
#define VMXNET3_OM_NONE 0
#define VMXNET3_OM_ENCAP 1
#define VMXNET3_OM_CSUM 2
#define VMXNET3_OM_TSO 3
/* fields in TxDesc we access w/o using bit fields */
#define VMXNET3_TXD_EOP_SHIFT 12
#define VMXNET3_TXD_CQ_SHIFT 13
#define VMXNET3_TXD_GEN_SHIFT 14
#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
#define VMXNET3_HDR_COPY_SIZE 128
struct Vmxnet3_TxDataDesc {
u8 data[VMXNET3_HDR_COPY_SIZE];
};
typedef u8 Vmxnet3_RxDataDesc;
#define VMXNET3_TCD_GEN_SHIFT 31
#define VMXNET3_TCD_GEN_SIZE 1
#define VMXNET3_TCD_TXIDX_SHIFT 0
#define VMXNET3_TCD_TXIDX_SIZE 12
#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
struct Vmxnet3_TxCompDesc {
u32 txdIdx:12; /* Index of the EOP TxDesc */
u32 ext1:20;
__le32 ext2;
__le32 ext3;
u32 rsvd:24;
u32 type:7; /* completion type */
u32 gen:1; /* generation bit */
};
struct Vmxnet3_RxDesc {
__le64 addr;
#ifdef __BIG_ENDIAN_BITFIELD
u32 gen:1; /* Generation bit */
u32 rsvd:15;
u32 dtype:1; /* Descriptor type */
u32 btype:1; /* Buffer Type */
u32 len:14;
#else
u32 len:14;
u32 btype:1; /* Buffer Type */
u32 dtype:1; /* Descriptor type */
u32 rsvd:15;
u32 gen:1; /* Generation bit */
#endif
u32 ext1;
};
/* values of RXD.BTYPE */
#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
/* fields in RxDesc we access w/o using bit fields */
#define VMXNET3_RXD_BTYPE_SHIFT 14
#define VMXNET3_RXD_GEN_SHIFT 31
#define VMXNET3_RCD_HDR_INNER_SHIFT 13
struct Vmxnet3TSInfo {
u64 tsData:56;
u64 tsType:4;
u64 tsi:1; //bit to indicate to set ts
u64 pad:3;
u64 pad2;
};
struct Vmxnet3_TxTSDesc {
struct Vmxnet3TSInfo ts;
u64 pad[14];
};
struct Vmxnet3_RxTSDesc {
struct Vmxnet3TSInfo ts;
u64 pad[14];
};
struct Vmxnet3_RxCompDesc {
#ifdef __BIG_ENDIAN_BITFIELD
u32 ext2:1;
u32 cnc:1; /* Checksum Not Calculated */
u32 rssType:4; /* RSS hash type used */
u32 rqID:10; /* rx queue/ring ID */
u32 sop:1; /* Start of Packet */
u32 eop:1; /* End of Packet */
u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
/* bit 1: indicating rssType is based on inner header */
u32 rxdIdx:12; /* Index of the RxDesc */
#else
u32 rxdIdx:12; /* Index of the RxDesc */
u32 ext1:2; /* bit 0: indicating v4/v6/.. is for inner header */
/* bit 1: indicating rssType is based on inner header */
u32 eop
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